/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUMachineCFGStructurizer.cpp | 271 dbgs() << "Dest: " << printReg(Element.DestReg, TRI) in dump() 274 dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second) in dump() 504 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump() 505 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; in dump() 554 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump() 555 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; in dump() 699 LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) in storeLiveOutReg() 704 LLVM_DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n"); in storeLiveOutReg() 711 << "): " << printReg(Reg, TRI) << "\n"); in storeLiveOutReg() 722 LLVM_DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI) in storeLiveOutReg() [all …]
|
D | GCNRegBankReassign.cpp | 95 dbgs() << P->printReg(Reg) << " to banks "; in dump() 232 Printable printReg(unsigned Reg, unsigned SubReg = 0) const { in printReg() function in __anon3185b0a50111::GCNRegBankReassign 235 OS << llvm::printReg(Reg, TRI); in printReg() 239 OS << "<unassigned> " << llvm::printReg(Reg, TRI); in printReg() 241 OS << llvm::printReg(Reg, TRI) << '(' in printReg() 242 << llvm::printReg(VRM->getPhys(Reg), TRI) << ')'; in printReg() 518 dbgs() << "Potential reassignments of " << printReg(Reg, SubReg) in getFreeBanks() 549 LLVM_DEBUG(dbgs() << "Conflicting operands: " << printReg(Reg1, SubReg1) << in collectCandidates() 550 " and " << printReg(Reg2, SubReg2) << '\n'); in collectCandidates() 611 LLVM_DEBUG(dbgs() << "Trying register " << printReg(Reg) << '\n'); in scavengeReg() [all …]
|
D | GCNNSAReassign.cpp | 299 dbgs() << " " << llvm::printReg((VRM->getPhys(LI->reg)), TRI); in runOnMachineFunction() 336 << llvm::printReg((VRM->getPhys(Intervals.front()->reg)), TRI) in runOnMachineFunction() 338 << llvm::printReg((VRM->getPhys(Intervals.back()->reg)), TRI) in runOnMachineFunction()
|
/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | AMDGPUMachineCFGStructurizer.cpp | 271 dbgs() << "Dest: " << printReg(Element.DestReg, TRI) in dump() 274 dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second) in dump() 504 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump() 505 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; in dump() 554 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump() 555 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; in dump() 699 LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) in storeLiveOutReg() 704 LLVM_DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n"); in storeLiveOutReg() 711 << "): " << printReg(Reg, TRI) << "\n"); in storeLiveOutReg() 722 LLVM_DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI) in storeLiveOutReg() [all …]
|
D | GCNRegBankReassign.cpp | 94 dbgs() << P->printReg(Reg) << " to banks "; in dump() 255 Printable printReg(Register Reg, unsigned SubReg = 0) const { in printReg() function in __anonf8be67910111::GCNRegBankReassign 258 OS << llvm::printReg(Reg, TRI); in printReg() 262 OS << "<unassigned> " << llvm::printReg(Reg, TRI); in printReg() 264 OS << llvm::printReg(Reg, TRI) << '(' in printReg() 265 << llvm::printReg(VRM->getPhys(Reg), TRI) << ')'; in printReg() 580 dbgs() << "Potential reassignments of " << printReg(Reg, SubReg) in getFreeBanks() 611 LLVM_DEBUG(dbgs() << "Conflicting operands: " << printReg(Reg1, SubReg1) << in collectCandidates() 612 " and " << printReg(Reg2, SubReg2) << '\n'); in collectCandidates() 674 LLVM_DEBUG(dbgs() << "Trying register " << printReg(Reg) << '\n'); in scavengeReg() [all …]
|
D | GCNNSAReassign.cpp | 307 << " " << llvm::printReg((VRM->getPhys(LI->reg())), TRI); in runOnMachineFunction() 345 << llvm::printReg((VRM->getPhys(Intervals.front()->reg())), TRI) in runOnMachineFunction() 347 << llvm::printReg((VRM->getPhys(Intervals.back()->reg())), TRI) in runOnMachineFunction()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | AggressiveAntiDepBreaker.cpp | 144 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker() 219 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe() 326 dbgs() << header << printReg(Reg, TRI); in HandleLastUse() 342 dbgs() << header << printReg(Reg, TRI); in HandleLastUse() 345 LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" in HandleLastUse() 381 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in PrescanInstruction() 402 << printReg(AliasReg, TRI) << ")"); in PrescanInstruction() 477 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in ScanInstruction() 513 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); in ScanInstruction() 516 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in ScanInstruction() [all …]
|
D | RegAllocFast.cpp | 317 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) in spill() 318 << " in " << printReg(AssignedReg, TRI)); in spill() 345 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " in reload() 346 << printReg(PhysReg, TRI) << '\n'); in reload() 562 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) in calcSpillCost() 572 LLVM_DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding " in calcSpillCost() 573 << printReg(PhysReg, TRI) << " is reserved already.\n"); in calcSpillCost() 584 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n"); in calcSpillCost() 613 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " in assignVirtToPhysReg() 614 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg() [all …]
|
D | LiveRegMatrix.cpp | 105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign() 106 << printReg(PhysReg, TRI) << ':'); in assign() 123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " in unassign() 124 << printReg(PhysReg, TRI) << ':'); in unassign()
|
D | RegAllocGreedy.cpp | 780 LLVM_DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n'); in tryAssign() 799 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " in tryAssign() 829 << printReg(PrevReg, TRI) << " to " in canReassign() 830 << printReg(PhysReg, TRI) << '\n'); in canReassign() 1057 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) in evictInterference() 1152 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " in tryEvict() 1153 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict() 1911 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); in calculateRegionSplitCost() 1914 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; in calculateRegionSplitCost() 1922 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in calculateRegionSplitCost() [all …]
|
D | TargetRegisterInfo.cpp | 73 dbgs() << "Error: Super register " << printReg(*SR, this) in checkAllSuperRegsMarked() 74 << " of reserved register " << printReg(Reg, this) in checkAllSuperRegsMarked() 89 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() function 521 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
|
/external/llvm-project/llvm/lib/CodeGen/ |
D | AggressiveAntiDepBreaker.cpp | 139 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker() 214 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe() 321 dbgs() << header << printReg(Reg, TRI); in HandleLastUse() 337 dbgs() << header << printReg(Reg, TRI); in HandleLastUse() 340 LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" in HandleLastUse() 376 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in PrescanInstruction() 397 << printReg(AliasReg, TRI) << ")"); in PrescanInstruction() 472 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in ScanInstruction() 508 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); in ScanInstruction() 511 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in ScanInstruction() [all …]
|
D | RegAllocFast.cpp | 390 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) in spill() 391 << " in " << printReg(AssignedReg, TRI)); in spill() 435 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " in reload() 436 << printReg(PhysReg, TRI) << '\n'); in reload() 567 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg() 581 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n'); in freePhysReg() 600 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost() 650 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " in assignVirtToPhysReg() 651 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg() 707 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg) in allocVirtReg() [all …]
|
D | LiveRegMatrix.cpp | 105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " in assign() 106 << printReg(PhysReg, TRI) << ':'); in assign() 123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI) in unassign() 124 << " from " << printReg(PhysReg, TRI) << ':'); in unassign()
|
D | FixupStatepointCallerSaved.cpp | 153 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI) in performCopyPropagation() 260 << printReg(Reg, &TRI) << " at " in getFrameIndex() 291 << printReg(Reg, &TRI) << " at landing pad " in getFrameIndex() 391 LLVM_DEBUG(dbgs() << "Will spill " << printReg(Reg, &TRI) << " at index " in findRegistersToSpill() 412 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, &TRI) << " to FI " << FI in spillRegisters() 456 LLVM_DEBUG(dbgs() << "Reloading " << printReg(Reg, &TRI) << " from FI " in insertReloads()
|
D | RegAllocGreedy.cpp | 786 LLVM_DEBUG(dbgs() << "missed hint " << printReg(PhysHint, TRI) << '\n'); in tryAssign() 806 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " in tryAssign() 837 << printReg(PrevReg, TRI) << " to " in canReassign() 838 << printReg(PhysReg, TRI) << '\n'); in canReassign() 1064 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) in evictInterference() 1160 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " in tryEvict() 1161 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict() 1901 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); in calculateRegionSplitCost() 1904 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; in calculateRegionSplitCost() 1912 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in calculateRegionSplitCost() [all …]
|
D | TargetRegisterInfo.cpp | 93 dbgs() << "Error: Super register " << printReg(*SR, this) in checkAllSuperRegsMarked() 94 << " of reserved register " << printReg(Reg, this) in checkAllSuperRegsMarked() 109 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() function 539 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
|
/external/llvm/lib/CodeGen/ |
D | MIRPrinter.cpp | 149 static void printReg(unsigned Reg, raw_ostream &OS, in printReg() function 162 static void printReg(unsigned Reg, yaml::StringValue &Dest, in printReg() function 165 printReg(Reg, OS, TRI); in printReg() 226 printReg(PreferredReg, VReg.PreferredRegister, TRI); in convert() 233 printReg(I->first, LiveIn.Register, TRI); in convert() 235 printReg(I->second, LiveIn.VirtualRegister, TRI); in convert() 247 printReg(I, Reg, TRI); in convert() 335 printReg(CSInfo.getReg(), Reg, TRI); in convertStackObjects() 494 printReg(LI.PhysReg, OS, TRI); in print() 773 printReg(Op.getReg(), OS, TRI); in print() [all …]
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64A57FPLoadBalancing.cpp | 543 LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); in colorChain() 617 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction() 637 << printReg(AccumReg, TRI) << " in MI " << *MI); in scanInstruction() 663 << printReg(DestReg, TRI) << "\n"); in scanInstruction() 691 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) in maybeKillChain() 703 << printReg(I->first, TRI) << "\n"); in maybeKillChain()
|
D | AArch64PBQPRegAlloc.cpp | 249 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) in addInterChainConstraint() 250 << " to " << printReg(Rd, TRI) << '\n';); in addInterChainConstraint() 255 LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) in addInterChainConstraint() 342 LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; in apply()
|
/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64A57FPLoadBalancing.cpp | 543 LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); in colorChain() 617 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction() 637 << printReg(AccumReg, TRI) << " in MI " << *MI); in scanInstruction() 663 << printReg(DestReg, TRI) << "\n"); in scanInstruction() 691 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) in maybeKillChain() 703 << printReg(I->first, TRI) << "\n"); in maybeKillChain()
|
D | AArch64PBQPRegAlloc.cpp | 249 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) in addInterChainConstraint() 250 << " to " << printReg(Rd, TRI) << '\n';); in addInterChainConstraint() 255 LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) in addInterChainConstraint() 342 LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; in apply()
|
/external/llvm-project/llvm/lib/Target/ARM/ |
D | MVEVPTOptimisationsPass.cpp | 515 << "Replacing all uses of '" << printReg(Result) in ReduceOldVCCRValueUses() 516 << "' with '" << printReg(LastVPNOTResult) << "'\n"); in ReduceOldVCCRValueUses() 525 LLVM_DEBUG(dbgs() << "Replacing use of '" << printReg(VCCRValue) in ReduceOldVCCRValueUses() 526 << "' with '" << printReg(LastVPNOTResult) in ReduceOldVCCRValueUses() 539 << printReg(OppositeVCCRValue) << "' with '" in ReduceOldVCCRValueUses() 540 << printReg(LastVPNOTResult) << " for instr: "; in ReduceOldVCCRValueUses()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonGenInsert.cpp | 194 OS << ' ' << printReg(R, P.TRI); in operator <<() 435 OS << printReg(*I, P.TRI); in operator <<() 488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<() 589 dbgs() << " " << printReg(I->first, HRI) << ":\n"; in dump_map() 802 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms() 867 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms() 872 dbgs() << " (" << printReg(LL[i].first, HRI) << ",@" in findRecordInsertForms() 919 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms() 920 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms() 1547 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n"; in runOnMachineFunction()
|
/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonGenInsert.cpp | 194 OS << ' ' << printReg(R, P.TRI); in operator <<() 435 OS << printReg(*I, P.TRI); in operator <<() 488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<() 589 dbgs() << " " << printReg(I->first, HRI) << ":\n"; in dump_map() 802 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms() 867 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms() 872 dbgs() << " (" << printReg(LL[i].first, HRI) << ",@" in findRecordInsertForms() 919 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms() 920 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms() 1547 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n"; in runOnMachineFunction()
|