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Searched refs:s_bfe_i32 (Results 1 – 25 of 31) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Didot8s.ll27 ; GFX7-NEXT: s_bfe_i32 s7, s5, 0x40000
28 ; GFX7-NEXT: s_bfe_i32 s6, s4, 0x40000
29 ; GFX7-NEXT: s_bfe_i32 s9, s5, 0x40004
33 ; GFX7-NEXT: s_bfe_i32 s8, s4, 0x40004
35 ; GFX7-NEXT: s_bfe_i32 s11, s5, 0x40008
37 ; GFX7-NEXT: s_bfe_i32 s10, s4, 0x40008
39 ; GFX7-NEXT: s_bfe_i32 s13, s5, 0x4000c
41 ; GFX7-NEXT: s_bfe_i32 s12, s4, 0x4000c
43 ; GFX7-NEXT: s_bfe_i32 s15, s5, 0x40010
45 ; GFX7-NEXT: s_bfe_i32 s14, s4, 0x40010
[all …]
Didot4s.ll23 ; GFX7-NEXT: s_bfe_i32 s9, s5, 0x80008
26 ; GFX7-NEXT: s_bfe_i32 s11, s5, 0x80010
28 ; GFX7-NEXT: s_bfe_i32 s8, s4, 0x80008
30 ; GFX7-NEXT: s_bfe_i32 s10, s4, 0x80010
52 ; GFX8-NEXT: s_bfe_i32 s7, s3, 0x80008
55 ; GFX8-NEXT: s_bfe_i32 s9, s3, 0x80010
57 ; GFX8-NEXT: s_bfe_i32 s6, s2, 0x80008
59 ; GFX8-NEXT: s_bfe_i32 s8, s2, 0x80010
84 ; GFX9-NODL-NEXT: s_bfe_i32 s7, s3, 0x80008
87 ; GFX9-NODL-NEXT: s_bfe_i32 s9, s3, 0x80010
[all …]
Dsetcc-limit-load-shrink.ll5 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
18 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
31 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
44 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
Dsext-in-reg.ll11 ; GCN: s_bfe_i32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000
138 ; XGCN: s_bfe_i32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288
259 ; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
278 ; GCN-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
279 ; GCN-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
300 ; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
301 ; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
317 ; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
318 ; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
319 ; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
[all …]
Dsint_to_fp.f64.ll77 ; VI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x80000
Dsign_extend.ll349 ; SI-NEXT: s_bfe_i32 s2, s0, 0x80010
350 ; SI-NEXT: s_bfe_i32 s3, s0, 0x80008
374 ; VI-NEXT: s_bfe_i32 s2, s0, 0x80010
Dload-constant-i8.ll184 ; GCN-DAG: s_bfe_i32
185 ; GCN-DAG: s_bfe_i32
186 ; GCN-DAG: s_bfe_i32
Damdgpu-codegenprepare-idiv.ll643 ; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008
701 ; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008
2565 ; GCN-NEXT: s_bfe_i32 s1, s0, 0x30008
2567 ; GCN-NEXT: s_bfe_i32 s0, s0, 0x30000
2624 ; GCN-NEXT: s_bfe_i32 s1, s0, 0x30008
2626 ; GCN-NEXT: s_bfe_i32 s3, s0, 0x30000
3561 ; GCN-NEXT: s_bfe_i32 s3, s0, 0xf0000
3565 ; GCN-NEXT: s_bfe_i32 s1, s2, 0xf0000
3569 ; GCN-NEXT: s_bfe_i32 s0, s0, 0xf000f
3580 ; GCN-NEXT: s_bfe_i32 s1, s2, 0xf000f
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.sbfe.ll20 ; GFX6-NEXT: s_bfe_i32 s0, s0, s1
55 ; GFX6-NEXT: s_bfe_i32 s0, s2, s0
75 ; GFX6-NEXT: s_bfe_i32 s0, s2, s0
96 ; GFX6-NEXT: s_bfe_i32 s0, 0x7b, s0
115 ; GFX6-NEXT: s_bfe_i32 s0, s0, 0x80002
135 ; GFX6-NEXT: s_bfe_i32 s0, s2, s0
152 ; GFX6-NEXT: s_bfe_i32 s0, s0, 8
172 ; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1f0001
194 ; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1f0000
216 ; GFX6-NEXT: s_bfe_i32 s0, s0, 0x1001f
[all …]
Dashr.ll119 ; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000
129 ; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000
Dllvm.amdgcn.ubfe.ll426 ; GFX6-NEXT: s_bfe_i32 s0, s0, 0x10000
Dssubsat.ll1067 ; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
1068 ; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000
1071 ; GFX8-NEXT: s_bfe_i32 s1, s1, 0x180000
Dsaddsat.ll1067 ; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
1068 ; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000
1071 ; GFX8-NEXT: s_bfe_i32 s1, s1, 0x180000
/external/llvm/test/CodeGen/AMDGPU/
Dsext-in-reg.ll10 ; SI: s_bfe_i32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000
137 ; XSI: s_bfe_i32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288
236 ; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
255 ; SI-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
256 ; SI-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
277 ; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
278 ; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
294 ; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
295 ; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
296 ; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
[all …]
Dsign_extend.ll68 ; GCN-DAG: s_bfe_i32 [[EXT1:s[0-9]+]], [[VAL]], 0x80008
69 ; GCN-DAG: s_bfe_i32 [[EXT2:s[0-9]+]], [[VAL]], 0x80010
Dload-constant-i8.ll167 ; GCN-DAG: s_bfe_i32
168 ; GCN-DAG: s_bfe_i32
169 ; GCN-DAG: s_bfe_i32
/external/llvm/test/MC/AMDGPU/
Dsop2.s147 s_bfe_i32 s2, s4, s6 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dsop2.s201 s_bfe_i32 s2, s4, s6 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt81 # VI: s_bfe_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x93]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt81 # VI: s_bfe_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x93]
Dgfx8_dasm_all.txt19770 # CHECK: s_bfe_i32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0x93]
19773 # CHECK: s_bfe_i32 s101, s1, s2 ; encoding: [0x01,0x02,0x65,0x93]
19776 # CHECK: s_bfe_i32 flat_scratch_lo, s1, s2 ; encoding: [0x01,0x02,0x66,0x93]
19779 # CHECK: s_bfe_i32 flat_scratch_hi, s1, s2 ; encoding: [0x01,0x02,0x67,0x93]
19782 # CHECK: s_bfe_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x93]
19785 # CHECK: s_bfe_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x93]
19788 # CHECK: s_bfe_i32 tba_lo, s1, s2 ; encoding: [0x01,0x02,0x6c,0x93]
19791 # CHECK: s_bfe_i32 tba_hi, s1, s2 ; encoding: [0x01,0x02,0x6d,0x93]
19794 # CHECK: s_bfe_i32 tma_lo, s1, s2 ; encoding: [0x01,0x02,0x6e,0x93]
19797 # CHECK: s_bfe_i32 tma_hi, s1, s2 ; encoding: [0x01,0x02,0x6f,0x93]
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td560 def S_BFE_I32 : SOP2_32 <"s_bfe_i32">;
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSOPInstructions.td613 def S_BFE_I32 : SOP2_32 <"s_bfe_i32">;
/external/mesa3d/src/amd/compiler/
Daco_instruction_selection.cpp647 aco_opcode op = mode == sgpr_extract_zext ? aco_opcode::s_bfe_u32 : aco_opcode::s_bfe_i32; in extract_8_16_bit_sgpr_element()
2831 … aco_opcode opcode = instr->op == nir_op_ubfe ? aco_opcode::s_bfe_u32 : aco_opcode::s_bfe_i32; in visit_alu_instr()
2849 bld.sop2(aco_opcode::s_bfe_i32, Definition(dst), bld.def(s1, scc), base, extract); in visit_alu_instr()
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td309 defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>;

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