| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | mul.ll | 48 ; GCN: s_mul_i32
76 ; GCN-DAG: s_mul_i32
112 ; FUNC-LABEL: {{^}}s_mul_i32:
115 ; GCN: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
119 define amdgpu_kernel void @s_mul_i32(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b) …
144 ; GFX9_10-DAG: s_mul_i32
146 ; GFX9_10-DAG: s_mul_i32
147 ; GFX9_10-DAG: s_mul_i32
166 ; GCN: s_mul_i32
187 ; GCN-DAG: s_mul_i32
[all …]
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| D | llvm.mulo.ll | 143 ; SI-NEXT: s_mul_i32 s4, s1, s2
146 ; SI-NEXT: s_mul_i32 s5, s0, s3
149 ; SI-NEXT: s_mul_i32 s1, s1, s3
150 ; SI-NEXT: s_mul_i32 s0, s0, s2
172 ; GFX9-NEXT: s_mul_i32 s7, s0, s3
176 ; GFX9-NEXT: s_mul_i32 s6, s1, s2
183 ; GFX9-NEXT: s_mul_i32 s1, s1, s3
188 ; GFX9-NEXT: s_mul_i32 s2, s0, s2
214 ; SI-NEXT: s_mul_i32 s4, s1, s2
217 ; SI-NEXT: s_mul_i32 s5, s0, s3
[all …]
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| D | codegen-prepare-addrmode-sext.ll | 9 ; SI-LLC: s_mul_i32
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| D | s_mulk_i32.ll | 35 ; SI: s_mul_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8001{{$}}
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| D | atomic_optimizations_raw_buffer.ll | 40 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
111 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
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| D | atomic_optimizations_struct_buffer.ll | 40 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
124 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
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| D | mul_uint24-amdgcn.ll | 24 ; VI: s_mul_i32 [[MUL:s[0-9]+]]
56 ; VI: s_mul_i32
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| D | atomic_optimizations_buffer.ll | 41 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
143 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
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| D | atomic_optimizations_global_pointer.ll | 38 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
146 ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
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| D | llvm.amdgcn.sendmsg.ll | 137 ; TODO: This should use s_mul_i32 instead of v_mul_u32_u24 + v_readfirstlane!
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| D | 32-bit-local-address-space.ll | 73 ; SI: s_mul_i32
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| D | atomic_optimizations_local_pointer.ll | 191 ; GFX7LESS-NEXT: s_mul_i32 s3, s2, s3
224 ; GFX8-NEXT: s_mul_i32 s1, s0, s1
257 ; GFX9-NEXT: s_mul_i32 s1, s0, s1
291 ; GFX1064-NEXT: s_mul_i32 s1, s0, s1
326 ; GFX1032-NEXT: s_mul_i32 s2, s0, s2
1262 ; GFX7LESS-NEXT: s_mul_i32 s7, s3, s6
1265 ; GFX7LESS-NEXT: s_mul_i32 s6, s2, s6
1307 ; GFX8-NEXT: s_mul_i32 s7, s3, s6
1308 ; GFX8-NEXT: s_mul_i32 s6, s2, s6
1349 ; GFX9-NEXT: s_mul_i32 s7, s3, s6
[all …]
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | mul.ll | 9 ; GFX7-NEXT: s_mul_i32 s0, s0, s1
17 ; GFX8-NEXT: s_mul_i32 s0, s0, s1
25 ; GFX9-NEXT: s_mul_i32 s0, s0, s1
59 ; GFX7-NEXT: s_mul_i32 s0, s0, s1
68 ; GFX8-NEXT: s_mul_i32 s0, s0, s1
77 ; GFX9-NEXT: s_mul_i32 s0, s0, s1
113 ; GFX7-NEXT: s_mul_i32 s0, s0, s1
122 ; GFX8-NEXT: s_mul_i32 s0, s0, s1
131 ; GFX9-NEXT: s_mul_i32 s0, s0, s1
166 define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) {
[all …]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mul.ll | 46 ; SI: s_mul_i32
74 ; SI-DAG: s_mul_i32
110 ; FUNC-LABEL: {{^}}s_mul_i32:
113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
117 define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
159 ; SI: s_mul_i32
180 ; SI-DAG: s_mul_i32
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| D | codegen-prepare-addrmode-sext.ll | 9 ; SI-LLC: s_mul_i32
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| D | s_mulk_i32.ll | 35 ; SI: s_mul_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8001{{$}}
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| D | 32-bit-local-address-space.ll | 71 ; SI: s_mul_i32
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| /external/llvm/test/MC/AMDGPU/ |
| D | trap.s | 89 s_mul_i32 ttmp8, 0x00000324, ttmp8 label
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| D | sop2.s | 139 s_mul_i32 s2, s4, s6 label
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| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | trap.s | 115 s_mul_i32 ttmp8, 0x00000324, ttmp8 label
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| D | sop2.s | 191 s_mul_i32 s2, s4, s6 label
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sop2_vi.txt | 75 # VI: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
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| D | trap_vi.txt | 67 # VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
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| /external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sop2_vi.txt | 75 # VI: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
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| D | trap_vi.txt | 67 # VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
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