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Searched refs:s_xor_b64 (Results 1 – 25 of 89) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dssubsat.ll58 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
82 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
96 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
143 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
150 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
206 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
213 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
220 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
283 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
290 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
10 ; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
13 ; The check for an s_xor_b64 is just to check that this test tests what it is
14 ; supposed to test. If the s_xor_b64 disappears due to some other case, it does
20 ; CHECK: s_xor_b64
Dsaddsat.ll58 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
82 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
96 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
143 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
150 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
205 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
212 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
219 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
282 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
289 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
Dsi-lower-control-flow-kill.ll5 ; GCN-NEXT: s_xor_b64 s[{{[0-9:]+}}], exec, [[SAVEEXEC]]
21 ; GCN-NEXT: s_xor_b64 s[{{[0-9:]+}}], exec, [[SAVEEXEC]]
47 ; GCN-NEXT: s_xor_b64 s[{{[0-9:]+}}], exec, [[SAVEEXEC]]
Dsaddo.ll29 ; SI-NEXT: s_xor_b64 s[4:5], s[6:7], vcc
49 ; VI-NEXT: s_xor_b64 s[0:1], s[8:9], vcc
71 ; GFX9-NEXT: s_xor_b64 s[0:1], s[8:9], vcc
102 ; SI-NEXT: s_xor_b64 s[0:1], s[10:11], vcc
124 ; VI-NEXT: s_xor_b64 s[0:1], s[2:3], vcc
180 ; SI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
204 ; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
252 ; SI-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
279 ; VI-NEXT: s_xor_b64 s[0:1], s[2:3], vcc
299 ; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], vcc
[all …]
Dxor3-i1-const.ll5 ; GCN: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1
6 ; GCN: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1
Dbfi_int.ll140 ; GCN: s_xor_b64
142 ; GCN: s_xor_b64
154 ; GCN: s_xor_b64
156 ; GCN: s_xor_b64
Delse.ll7 ; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
33 ; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
Dxor.ll45 ; SI: s_xor_b64 [[XOR:vcc]], [[CMP1]], [[CMP0]]
123 ; SI: s_xor_b64
155 ; SI: s_xor_b64
191 ; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
222 ; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -8
Dimage-sample-waterfall.ll27 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]]
51 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]]
Dloop_exit_with_xor.ll9 ; GCN: s_xor_b64 [[REG1:[^ ,]*]], {{[^ ,]*, -1$}}
63 ; GCN: s_xor_b64 [[REG1:[^ ,]*]], {{[^ ,]*, -1$}}
Dvalu-i1.ll15 ; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]]
26 ; SI-NEXT: s_xor_b64 exec, exec, [[SAVE3]]
120 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
125 ; SI-NEXT: s_xor_b64 exec, exec
Dsgpr-control-flow.ll115 ; SI-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
124 ; SI-NEXT: s_xor_b64 exec, exec, s[2:3]
163 ; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
178 ; SI-NEXT: s_xor_b64 exec, exec, s[2:3]
Dmubuf-legalize-operands.ll21 ; W64: s_xor_b64 exec, exec, [[AND]]
64 ; W64: s_xor_b64 exec, exec, [[SAVE]]
82 ; W64: s_xor_b64 exec, exec, [[SAVE]]
155 ; W64: s_xor_b64 exec, exec, [[SAVE]]
176 ; W64: s_xor_b64 exec, exec, [[SAVE]]
266 ; W64-O0: s_xor_b64 exec, exec, [[SAVE]]
305 ; W64-O0: s_xor_b64 exec, exec, [[SAVE]]
Dcollapse-endcf.ll85 ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
91 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
129 ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
141 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
Dsub_i1.ll7 ; WAVE64: s_xor_b64
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dxnor.ll40 ; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
110 ; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
111 ; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
116 ; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
123 ; GFX8-NEXT: s_xor_b64 s[0:1], s[2:3], s[4:5]
124 ; GFX8-NEXT: s_xor_b64 s[2:3], s[6:7], s[4:5]
137 ; GFX900-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
138 ; GFX900-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
145 ; GFX906-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
146 ; GFX906-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
[all …]
Dlocalizer.ll158 ; GFX9-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
160 ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
175 ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
/external/llvm/test/CodeGen/AMDGPU/
Di1-copy-phi.ll7 ; SI: s_xor_b64
11 ; SI: s_xor_b64
Dsi-lower-control-flow-unreachable-block.ll6 ; GCN: s_xor_b64
31 ; GCN: s_xor_b64
Dvalu-i1.ll48 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
74 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
117 ; SI: s_xor_b64 [[OUTER_CMP_SREG]], exec, [[OUTER_CMP_SREG]]
133 ; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]]
Dsi-annotate-cfg-loop-assert.ll5 ; CHECK s_xor_b64
Dxor.ll45 ; SI: s_xor_b64 [[XOR:vcc]], [[CMP0]], [[CMP1]]
123 ; SI: s_xor_b64
155 ; SI: s_xor_b64
/external/llvm/test/MC/AMDGPU/
Dsop2.s63 s_xor_b64 s[2:3], s[4:5], s[6:7] label

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