1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
3;
4; Most SALU instructions ignore control flow, so we need to make sure
5; they don't overwrite values from other blocks.
6
7; If the branch decision is made based on a value in an SGPR then all
8; threads will execute the same code paths, so we don't need to worry
9; about instructions in different blocks overwriting each other.
10
11define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
12; SI-LABEL: sgpr_if_else_salu_br:
13; SI:       ; %bb.0: ; %entry
14; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
15; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xb
16; SI-NEXT:    s_load_dword s0, s[0:1], 0xf
17; SI-NEXT:    s_waitcnt lgkmcnt(0)
18; SI-NEXT:    s_cmp_lg_u32 s8, 0
19; SI-NEXT:    s_cbranch_scc0 BB0_2
20; SI-NEXT:  ; %bb.1: ; %else
21; SI-NEXT:    s_add_i32 s0, s11, s0
22; SI-NEXT:    s_cbranch_execz BB0_3
23; SI-NEXT:    s_branch BB0_4
24; SI-NEXT:  BB0_2:
25; SI-NEXT:    ; implicit-def: $sgpr0
26; SI-NEXT:  BB0_3: ; %if
27; SI-NEXT:    s_sub_i32 s0, s9, s10
28; SI-NEXT:  BB0_4: ; %endif
29; SI-NEXT:    s_add_i32 s0, s0, s8
30; SI-NEXT:    s_mov_b32 s7, 0xf000
31; SI-NEXT:    s_mov_b32 s6, -1
32; SI-NEXT:    v_mov_b32_e32 v0, s0
33; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
34; SI-NEXT:    s_endpgm
35
36entry:
37  %0 = icmp eq i32 %a, 0
38  br i1 %0, label %if, label %else
39
40if:
41  %1 = sub i32 %b, %c
42  br label %endif
43
44else:
45  %2 = add i32 %d, %e
46  br label %endif
47
48endif:
49  %3 = phi i32 [%1, %if], [%2, %else]
50  %4 = add i32 %3, %a
51  store i32 %4, i32 addrspace(1)* %out
52  ret void
53}
54
55define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
56; SI-LABEL: sgpr_if_else_salu_br_opt:
57; SI:       ; %bb.0: ; %entry
58; SI-NEXT:    s_load_dword s2, s[0:1], 0x13
59; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
60; SI-NEXT:    s_waitcnt lgkmcnt(0)
61; SI-NEXT:    s_cmp_lg_u32 s2, 0
62; SI-NEXT:    s_cbranch_scc0 BB1_2
63; SI-NEXT:  ; %bb.1: ; %else
64; SI-NEXT:    s_load_dword s3, s[0:1], 0x2e
65; SI-NEXT:    s_load_dword s6, s[0:1], 0x37
66; SI-NEXT:    s_waitcnt lgkmcnt(0)
67; SI-NEXT:    s_add_i32 s3, s3, s6
68; SI-NEXT:    s_cbranch_execz BB1_3
69; SI-NEXT:    s_branch BB1_4
70; SI-NEXT:  BB1_2:
71; SI-NEXT:    ; implicit-def: $sgpr3
72; SI-NEXT:  BB1_3: ; %if
73; SI-NEXT:    s_load_dword s3, s[0:1], 0x1c
74; SI-NEXT:    s_load_dword s0, s[0:1], 0x25
75; SI-NEXT:    s_waitcnt lgkmcnt(0)
76; SI-NEXT:    s_add_i32 s3, s3, s0
77; SI-NEXT:  BB1_4: ; %endif
78; SI-NEXT:    s_add_i32 s0, s3, s2
79; SI-NEXT:    s_mov_b32 s7, 0xf000
80; SI-NEXT:    s_mov_b32 s6, -1
81; SI-NEXT:    v_mov_b32_e32 v0, s0
82; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
83; SI-NEXT:    s_endpgm
84
85entry:
86  %cmp0 = icmp eq i32 %a, 0
87  br i1 %cmp0, label %if, label %else
88
89if:
90  %add0 = add i32 %b, %c
91  br label %endif
92
93else:
94  %add1 = add i32 %d, %e
95  br label %endif
96
97endif:
98  %phi = phi i32 [%add0, %if], [%add1, %else]
99  %add2 = add i32 %phi, %a
100  store i32 %add2, i32 addrspace(1)* %out
101  ret void
102}
103
104; The two S_ADD instructions should write to different registers, since
105; different threads will take different control flow paths.
106define amdgpu_kernel void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
107; SI-LABEL: sgpr_if_else_valu_br:
108; SI:       ; %bb.0: ; %entry
109; SI-NEXT:    v_cvt_f32_u32_e32 v0, v0
110; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
111; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xc
112; SI-NEXT:    ; implicit-def: $sgpr6
113; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v0
114; SI-NEXT:    s_and_saveexec_b64 s[8:9], vcc
115; SI-NEXT:    s_xor_b64 s[8:9], exec, s[8:9]
116; SI-NEXT:    s_cbranch_execz BB2_2
117; SI-NEXT:  ; %bb.1: ; %else
118; SI-NEXT:    s_waitcnt lgkmcnt(0)
119; SI-NEXT:    s_add_i32 s6, s2, s3
120; SI-NEXT:  BB2_2: ; %Flow
121; SI-NEXT:    s_waitcnt lgkmcnt(0)
122; SI-NEXT:    s_or_saveexec_b64 s[2:3], s[8:9]
123; SI-NEXT:    v_mov_b32_e32 v0, s6
124; SI-NEXT:    s_xor_b64 exec, exec, s[2:3]
125; SI-NEXT:  ; %bb.3: ; %if
126; SI-NEXT:    s_add_i32 s0, s0, s1
127; SI-NEXT:    v_mov_b32_e32 v0, s0
128; SI-NEXT:  ; %bb.4: ; %endif
129; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
130; SI-NEXT:    s_mov_b32 s7, 0xf000
131; SI-NEXT:    s_mov_b32 s6, -1
132; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
133; SI-NEXT:    s_endpgm
134entry:
135  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
136  %tid_f = uitofp i32 %tid to float
137  %tmp1 = fcmp ueq float %tid_f, 0.0
138  br i1 %tmp1, label %if, label %else
139
140if:
141  %tmp2 = add i32 %b, %c
142  br label %endif
143
144else:
145  %tmp3 = add i32 %d, %e
146  br label %endif
147
148endif:
149  %tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
150  store i32 %tmp4, i32 addrspace(1)* %out
151  ret void
152}
153
154define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
155; SI-LABEL: sgpr_if_else_valu_cmp_phi_br:
156; SI:       ; %bb.0: ; %entry
157; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
158; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
159; SI-NEXT:    s_mov_b32 s10, 0
160; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
161; SI-NEXT:    ; implicit-def: $sgpr0_sgpr1
162; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
163; SI-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
164; SI-NEXT:    s_cbranch_execz BB3_2
165; SI-NEXT:  ; %bb.1: ; %else
166; SI-NEXT:    s_mov_b32 s11, 0xf000
167; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
168; SI-NEXT:    v_mov_b32_e32 v2, 0
169; SI-NEXT:    s_waitcnt lgkmcnt(0)
170; SI-NEXT:    buffer_load_dword v1, v[1:2], s[8:11], 0 addr64
171; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
172; SI-NEXT:    s_waitcnt vmcnt(0)
173; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v1
174; SI-NEXT:    s_and_b64 s[8:9], vcc, exec
175; SI-NEXT:    s_or_b64 s[0:1], s[0:1], s[8:9]
176; SI-NEXT:  BB3_2: ; %Flow
177; SI-NEXT:    s_or_saveexec_b64 s[2:3], s[2:3]
178; SI-NEXT:    s_xor_b64 exec, exec, s[2:3]
179; SI-NEXT:    s_cbranch_execz BB3_4
180; SI-NEXT:  ; %bb.3: ; %if
181; SI-NEXT:    s_mov_b32 s11, 0xf000
182; SI-NEXT:    s_mov_b32 s10, 0
183; SI-NEXT:    s_waitcnt lgkmcnt(0)
184; SI-NEXT:    s_mov_b64 s[8:9], s[6:7]
185; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
186; SI-NEXT:    v_mov_b32_e32 v1, 0
187; SI-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
188; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
189; SI-NEXT:    s_waitcnt vmcnt(0)
190; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
191; SI-NEXT:    s_and_b64 s[6:7], vcc, exec
192; SI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
193; SI-NEXT:  BB3_4: ; %endif
194; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
195; SI-NEXT:    s_waitcnt lgkmcnt(0)
196; SI-NEXT:    s_mov_b32 s7, 0xf000
197; SI-NEXT:    s_mov_b32 s6, -1
198; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[0:1]
199; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
200; SI-NEXT:    s_endpgm
201entry:
202  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
203  %tmp1 = icmp eq i32 %tid, 0
204  br i1 %tmp1, label %if, label %else
205
206if:
207  %gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
208  %a.val = load i32, i32 addrspace(1)* %gep.if
209  %cmp.if = icmp eq i32 %a.val, 0
210  br label %endif
211
212else:
213  %gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
214  %b.val = load i32, i32 addrspace(1)* %gep.else
215  %cmp.else = icmp slt i32 %b.val, 0
216  br label %endif
217
218endif:
219  %tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
220  %ext = sext i1 %tmp4 to i32
221  store i32 %ext, i32 addrspace(1)* %out
222  ret void
223}
224
225declare i32 @llvm.amdgcn.workitem.id.x() #0
226
227attributes #0 = { readnone }
228