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Searched refs:st1b (Results 1 – 25 of 71) sorted by relevance

123

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dst1b-diagnostics.s6 st1b z10.b, p4, [x8, #-9, MUL VL] label
11 st1b z18.b, p4, [x24, #8, MUL VL] label
16 st1b z11.h, p0, [x23, #-9, MUL VL] label
21 st1b z24.h, p3, [x1, #8, MUL VL] label
26 st1b z6.s, p5, [x23, #-9, MUL VL] label
31 st1b z16.s, p6, [x14, #8, MUL VL] label
36 st1b z26.d, p2, [x7, #-9, MUL VL] label
41 st1b z27.d, p1, [x12, #8, MUL VL] label
49 st1b z12.b, p8, [x27, #6, MUL VL] label
54 st1b z23.h, p8, [x20, #1, MUL VL] label
[all …]
Dst1b.s10 st1b z0.b, p0, [x0] label
16 st1b z0.h, p0, [x0] label
22 st1b z0.s, p0, [x0] label
28 st1b z0.d, p0, [x0] label
34 st1b { z0.b }, p0, [x0] label
40 st1b { z0.h }, p0, [x0] label
46 st1b { z0.s }, p0, [x0] label
52 st1b { z0.d }, p0, [x0] label
58 st1b { z31.b }, p7, [sp, #-1, mul vl] label
64 st1b { z21.b }, p5, [x10, #5, mul vl] label
[all …]
/external/arm-optimized-routines/string/aarch64/
Dstrcpy-sve.S43 st1b z0.b, p2, [x0, x2]
54 st1b z0.b, p0, [x0, x2]
60 st1b z0.b, p0, [x0, x2]
/external/llvm-project/libc/AOR_v20.02/string/aarch64/
Dstrcpy-sve.S46 st1b z0.b, p2, [x0, x2]
57 st1b z0.b, p0, [x0, x2]
63 st1b z0.b, p0, [x0, x2]
/external/llvm-project/llvm/test/CodeGen/VE/Scalar/
Dstackframe_align.ll29 ; CHECK-NEXT: st1b %s1, 9(, %s11)
52 ; CHECKFP-NEXT: st1b %s1, -7(, %s9)
85 ; CHECK-NEXT: st1b %s1, 8(, %s11)
108 ; CHECKFP-NEXT: st1b %s1, -8(, %s9)
141 ; CHECK-NEXT: st1b %s1, (, %s11)
164 ; CHECKFP-NEXT: st1b %s1, -16(, %s9)
202 ; CHECK-NEXT: st1b %s1, 192(, %s11)
228 ; CHECKFP-NEXT: st1b %s1, 192(, %s11)
266 ; CHECK-NEXT: st1b %s1, 192(, %s11)
292 ; CHECKFP-NEXT: st1b %s1, 192(, %s11)
[all …]
Dstackframe_size.ll36 ; CHECK-NEXT: st1b %s1, 8(, %s11)
64 ; CHECK-NEXT: st1b %s1, (, %s11)
92 ; CHECK-NEXT: st1b %s1, (, %s11)
120 ; CHECK-NEXT: st1b %s1, (, %s11)
148 ; CHECK-NEXT: st1b %s1, (, %s11)
176 ; CHECK-NEXT: st1b %s1, (, %s11)
206 ; CHECK-NEXT: st1b %s1, (, %s11)
Dstackframe_nocall.ll46 ; CHECK-NEXT: st1b %s1, (, %s11)
66 ; PIC-NEXT: st1b %s1, (, %s11)
119 ; CHECK-NEXT: st1b %s1, (, %s2)
166 ; PIC-NEXT: st1b %s1, (, %s2)
193 ; CHECK-NEXT: st1b %s1, (, %s0)
209 ; PIC-NEXT: st1b %s1, (, %s0)
239 ; CHECK-NEXT: st1b %s1, (, %s11)
269 ; PIC-NEXT: st1b %s1, (, %s11)
318 ; CHECK-NEXT: st1b %s1, (, %s2)
365 ; PIC-NEXT: st1b %s1, (, %s2)
Dstore.ll101 ; CHECK-NEXT: st1b %s1, (, %s0)
111 ; CHECK-NEXT: st1b %s1, (, %s0)
208 ; CHECK-NEXT: st1b %s0, (, %s11)
Datomic_store.ll68 ; CHECK-NEXT: st1b %s1, (, %s0)
80 ; CHECK-NEXT: st1b %s1, (, %s0)
91 ; CHECK-NEXT: st1b %s1, (, %s0)
221 ; CHECK-NEXT: st1b %s1, (, %s0)
234 ; CHECK-NEXT: st1b %s1, (, %s0)
246 ; CHECK-NEXT: st1b %s1, (, %s0)
382 ; CHECK-NEXT: st1b %s1, (, %s0)
396 ; CHECK-NEXT: st1b %s1, (, %s0)
409 ; CHECK-NEXT: st1b %s1, (, %s0)
Dfcopysign.ll80 ; CHECK-NEXT: st1b %s0, 15(, %s11)
135 ; CHECK-NEXT: st1b %s0, 15(, %s11)
191 ; CHECK-NEXT: st1b %s0, 15(, %s11)
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-masked-scatter-legalise.ll8 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]
9 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]
10 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]
11 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]
Dsve-st1-addressing-mode-reg-imm.ll14 ; CHECK-NEXT: st1b { z0.b }, p0, [x0, #-8, mul vl]
25 ; CHECK-NEXT: st1b { z0.b }, p0, [x0, #1, mul vl]
36 ; CHECK-NEXT: st1b { z0.b }, p0, [x0, #7, mul vl]
49 ; CHECK-NEXT: st1b { z0.b }, p0, [x8]
62 ; CHECK-NEXT: st1b { z0.b }, p0, [x8]
Dsve-gather-scatter-dag-combine.ll16 ; CHECK-NEXT: st1b { z0.d }, p1, [x0]
40 ; CHECK-NEXT: st1b { z1.d }, p1, [x0]
60 ; CHECK-NEXT: st1b { z0.d }, p1, [x0]
Dsve-intrinsics-st1-addressing-mode-reg-imm.ll13 ; CHECK: st1b { z0.b }, p0, [x0, #7, mul vl]
24 ; CHECK: st1b { z0.b }, p0, [x0, #1, mul vl]
35 ; CHECK: st1b { z0.b }, p0, [x0, #-8, mul vl]
47 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]]
59 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]]
70 ; CHECK: st1b { z0.s }, p0, [x0, #7, mul vl]
82 ; CHECK: st1b { z0.h }, p0, [x0, #1, mul vl]
94 ; CHECK: st1b { z0.d }, p0, [x0, #-7, mul vl]
Dsve-fixed-length-int-log.ll56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0]
71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0]
76 ; VBITS_LE_256-DAG: st1b { [[RES_1]].b }, [[PG]], [x0, x[[OFF_1]]]
91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0]
96 ; VBITS_LE_512-DAG: st1b { [[RES_1]].b }, [[PG]], [x0, x[[OFF_1]]]
101 ; VBITS_LE_256-DAG: st1b { [[RES_2]].b }, [[PG]], [x0, x[[OFF_2]]]
106 ; VBITS_LE_256-DAG: st1b { [[RES_3]].b }, [[PG]], [x0, x[[OFF_3]]]
121 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0]
126 ; VBITS_LE_1024-DAG: st1b { [[RES_1]].b }, [[PG]], [x0, x[[OFF_1]]]
131 ; VBITS_LE_512-DAG: st1b { [[RES_2]].b }, [[PG]], [x0, x[[OFF_2]]]
[all …]
Dsve-masked-ldst-trunc.ll13 ; CHECK-NEXT: st1b { z0.d }, p0, [x1]
40 ; CHECK-NEXT: st1b { z0.s }, p0, [x1]
58 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
Dsve-split-store.ll14 ; CHECK-NEXT: st1b { z0.s }, p0, [x0]
66 ; CHECK-NEXT: st1b { z0.d }, p0, [x0]
75 ; CHECK-NEXT: st1b { z1.b }, p1, [x0, #1, mul vl]
76 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
Dsve-fixed-length-int-arith.ll56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0]
71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0]
76 ; VBITS_LE_256-DAG: st1b { [[RES_1]].b }, [[PG]], [x0, x[[OFF_1]]]
91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0]
96 ; VBITS_LE_512-DAG: st1b { [[RES_1]].b }, [[PG]], [x0, x[[OFF_1]]]
101 ; VBITS_LE_256-DAG: st1b { [[RES_2]].b }, [[PG]], [x0, x[[OFF_2]]]
106 ; VBITS_LE_256-DAG: st1b { [[RES_3]].b }, [[PG]], [x0, x[[OFF_3]]]
121 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0]
126 ; VBITS_LE_1024-DAG: st1b { [[RES_1]].b }, [[PG]], [x0, x[[OFF_1]]]
131 ; VBITS_LE_512-DAG: st1b { [[RES_2]].b }, [[PG]], [x0, x[[OFF_2]]]
[all …]
Dsve-intrinsics-st1.ll14 ; CHECK: st1b { z0.b }, p0, [x0]
24 ; CHECK: st1b { z0.h }, p0, [x0]
35 ; CHECK: st1b { z0.s }, p0, [x0]
46 ; CHECK: st1b { z0.d }, p0, [x0]
Dsve-intrinsics-st1-addressing-mode-reg-reg.ll13 ; CHECK: st1b { z0.b }, p0, [x0, x1]
26 ; CHECK: st1b { z0.h }, p0, [x0, x1]
38 ; CHECK: st1b { z0.s }, p0, [x0, x1]
50 ; CHECK: st1b { z0.d }, p0, [x0, x1]
Dsve-fixed-length-int-shifts.ll53 ; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
68 ; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
80 ; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0]
81 ; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[OFFSET_HI]]
96 ; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
111 ; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
432 ; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
447 ; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
459 ; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0]
460 ; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[OFFSET_HI]]
[all …]
Dsve-fixed-length-int-immediates.ll21 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
92 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
160 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
229 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
304 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
373 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
444 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
512 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
581 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
653 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
[all …]
Dspillfill-sve.ll251 ; CHECK-DAG: st1b { z{{[01]}}.b }, p0, [sp]
252 ; CHECK-DAG: st1b { z{{[01]}}.b }, p0, [sp, #1, mul vl]
262 ; CHECK-DAG: st1b { z{{[01]}}.h }, p0, [sp]
263 ; CHECK-DAG: st1b { z{{[01]}}.h }, p0, [sp, #1, mul vl]
273 ; CHECK-DAG: st1b { z{{[01]}}.s }, p0, [sp, #3, mul vl]
274 ; CHECK-DAG: st1b { z{{[01]}}.s }, p0, [sp, #2, mul vl]
284 ; CHECK-DAG: st1b { z{{[01]}}.d }, p0, [sp, #7, mul vl]
285 ; CHECK-DAG: st1b { z{{[01]}}.d }, p0, [sp, #6, mul vl]
Dsve-intrinsics-scatter-stores-vector-base-imm-offset.ll15 ; CHECK: st1b { z0.s }, p0, [z1.s, #16]
27 ; CHECK: st1b { z0.d }, p0, [z1.d, #16]
129 ; CHECK-NEXT: st1b { z0.s }, p0, [x8, z1.s, uxtw]
142 ; CHECK-NEXT: st1b { z0.d }, p0, [x8, z1.d]
/external/llvm-project/llvm/test/MC/VE/
DST.s34 # CHECK-INST: st1b %s11, 20(%s10, %s11)
36 st1b %s11, 20(%s10, %s11) label

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