1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 3; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 4 5; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 6; WARN-NOT: warning 7 8; UNPREDICATED 9 10define void @store_promote_4i8(<vscale x 4 x i8> %data, <vscale x 4 x i8>* %a) { 11; CHECK-LABEL: store_promote_4i8: 12; CHECK: // %bb.0: 13; CHECK-NEXT: ptrue p0.s 14; CHECK-NEXT: st1b { z0.s }, p0, [x0] 15; CHECK-NEXT: ret 16 store <vscale x 4 x i8> %data, <vscale x 4 x i8>* %a 17 ret void 18} 19 20define void @store_split_i16(<vscale x 16 x i16> %data, <vscale x 16 x i16>* %a) { 21; CHECK-LABEL: store_split_i16: 22; CHECK: // %bb.0: 23; CHECK-NEXT: ptrue p0.h 24; CHECK-NEXT: st1h { z1.h }, p0, [x0, #1, mul vl] 25; CHECK-NEXT: st1h { z0.h }, p0, [x0] 26; CHECK-NEXT: ret 27 store <vscale x 16 x i16> %data, <vscale x 16 x i16>* %a 28 ret void 29} 30 31define void @store_split_16i32(<vscale x 16 x i32> %data, <vscale x 16 x i32>* %a) { 32; CHECK-LABEL: store_split_16i32: 33; CHECK: // %bb.0: 34; CHECK-NEXT: ptrue p0.s 35; CHECK-NEXT: st1w { z3.s }, p0, [x0, #3, mul vl] 36; CHECK-NEXT: st1w { z2.s }, p0, [x0, #2, mul vl] 37; CHECK-NEXT: st1w { z1.s }, p0, [x0, #1, mul vl] 38; CHECK-NEXT: st1w { z0.s }, p0, [x0] 39; CHECK-NEXT: ret 40 store <vscale x 16 x i32> %data, <vscale x 16 x i32>* %a 41 ret void 42} 43 44define void @store_split_16i64(<vscale x 16 x i64> %data, <vscale x 16 x i64>* %a) { 45; CHECK-LABEL: store_split_16i64: 46; CHECK: // %bb.0: 47; CHECK-NEXT: ptrue p0.d 48; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl] 49; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl] 50; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl] 51; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl] 52; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 53; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 54; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 55; CHECK-NEXT: st1d { z0.d }, p0, [x0] 56; CHECK-NEXT: ret 57 store <vscale x 16 x i64> %data, <vscale x 16 x i64>* %a 58 ret void 59} 60 61; MASKED 62 63define void @masked_store_promote_2i8(<vscale x 2 x i8> %data, <vscale x 2 x i8> *%a, <vscale x 2 x i1> %pg) { 64; CHECK-LABEL: masked_store_promote_2i8: 65; CHECK: // %bb.0: 66; CHECK-NEXT: st1b { z0.d }, p0, [x0] 67; CHECK-NEXT: ret 68 call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %data, <vscale x 2 x i8> *%a, i32 1, <vscale x 2 x i1> %pg) 69 ret void 70} 71 72define void @masked_store_split_32i8(<vscale x 32 x i8> %data, <vscale x 32 x i8> *%a, <vscale x 32 x i1> %pg) { 73; CHECK-LABEL: masked_store_split_32i8: 74; CHECK: // %bb.0: 75; CHECK-NEXT: st1b { z1.b }, p1, [x0, #1, mul vl] 76; CHECK-NEXT: st1b { z0.b }, p0, [x0] 77; CHECK-NEXT: ret 78 call void @llvm.masked.store.nxv32i8(<vscale x 32 x i8> %data, <vscale x 32 x i8> *%a, i32 1, <vscale x 32 x i1> %pg) 79 ret void 80} 81 82define void @masked_store_split_32i16(<vscale x 32 x i16> %data, <vscale x 32 x i16> *%a, <vscale x 32 x i1> %pg) { 83; CHECK-LABEL: masked_store_split_32i16: 84; CHECK: // %bb.0: 85; CHECK-NEXT: pfalse p2.b 86; CHECK-NEXT: zip2 p3.b, p1.b, p2.b 87; CHECK-NEXT: zip1 p1.b, p1.b, p2.b 88; CHECK-NEXT: st1h { z3.h }, p3, [x0, #3, mul vl] 89; CHECK-NEXT: zip2 p3.b, p0.b, p2.b 90; CHECK-NEXT: zip1 p0.b, p0.b, p2.b 91; CHECK-NEXT: st1h { z2.h }, p1, [x0, #2, mul vl] 92; CHECK-NEXT: st1h { z1.h }, p3, [x0, #1, mul vl] 93; CHECK-NEXT: st1h { z0.h }, p0, [x0] 94; CHECK-NEXT: ret 95 call void @llvm.masked.store.nxv32i16(<vscale x 32 x i16> %data, <vscale x 32 x i16> *%a, i32 1, <vscale x 32 x i1> %pg) 96 ret void 97} 98 99define void @masked_store_split_8i32(<vscale x 8 x i32> %data, <vscale x 8 x i32> *%a, <vscale x 8 x i1> %pg) { 100; CHECK-LABEL: masked_store_split_8i32: 101; CHECK: // %bb.0: 102; CHECK-NEXT: pfalse p1.b 103; CHECK-NEXT: zip2 p2.h, p0.h, p1.h 104; CHECK-NEXT: zip1 p0.h, p0.h, p1.h 105; CHECK-NEXT: st1w { z1.s }, p2, [x0, #1, mul vl] 106; CHECK-NEXT: st1w { z0.s }, p0, [x0] 107; CHECK-NEXT: ret 108 call void @llvm.masked.store.nxv8i32(<vscale x 8 x i32> %data, <vscale x 8 x i32> *%a, i32 1, <vscale x 8 x i1> %pg) 109 ret void 110} 111 112define void @masked_store_split_8i64(<vscale x 8 x i64> %data, <vscale x 8 x i64> *%a, <vscale x 8 x i1> %pg) { 113; CHECK-LABEL: masked_store_split_8i64: 114; CHECK: // %bb.0: 115; CHECK-NEXT: pfalse p1.b 116; CHECK-NEXT: zip2 p2.h, p0.h, p1.h 117; CHECK-NEXT: zip1 p0.h, p0.h, p1.h 118; CHECK-NEXT: zip2 p3.s, p2.s, p1.s 119; CHECK-NEXT: zip1 p2.s, p2.s, p1.s 120; CHECK-NEXT: st1d { z3.d }, p3, [x0, #3, mul vl] 121; CHECK-NEXT: st1d { z2.d }, p2, [x0, #2, mul vl] 122; CHECK-NEXT: zip2 p2.s, p0.s, p1.s 123; CHECK-NEXT: zip1 p0.s, p0.s, p1.s 124; CHECK-NEXT: st1d { z1.d }, p2, [x0, #1, mul vl] 125; CHECK-NEXT: st1d { z0.d }, p0, [x0] 126; CHECK-NEXT: ret 127 call void @llvm.masked.store.nxv8i64(<vscale x 8 x i64> %data, <vscale x 8 x i64> *%a, i32 1, <vscale x 8 x i1> %pg) 128 ret void 129} 130 131declare void @llvm.masked.store.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>*, i32, <vscale x 2 x i1>) 132declare void @llvm.masked.store.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>*, i32, <vscale x 32 x i1>) 133 134declare void @llvm.masked.store.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>*, i32, <vscale x 32 x i1>) 135 136declare void @llvm.masked.store.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>*, i32, <vscale x 8 x i1>) 137 138declare void @llvm.masked.store.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>*, i32, <vscale x 8 x i1>) 139