| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 558 sub_lo, // 9
700 { 0, 32 }, // sub_lo
3935 …sp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub…
3948 LaneBitmask(0x00000001), // sub_lo
4059 0x00000001, 0x00000120, 0x0000001f, // sub_lo
4065 0x00000001, 0x00000120, 0x0000001f, // sub_lo
4150 0x00000000, 0x02010000, 0x00000000, // sub_lo
4207 0x00000000, 0x02000000, 0x00000000, // sub_lo
4321 0x00000000, 0x00000000, 0x00000020, // sub_lo
6161 { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 574 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi()
599 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
602 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
617 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64()
679 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
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| D | MipsRegisterInfo.td | 16 def sub_lo : SubRegIndex<32>;
56 let SubRegIndices = [sub_lo, sub_hi];
62 let SubRegIndices = [sub_lo, sub_hi];
75 let SubRegIndices = [sub_lo, sub_hi];
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| D | MipsSEFrameLowering.cpp | 191 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
248 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC()
439 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); in emitPrologue()
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| D | MipsMSAInstrInfo.td | 3758 sub_lo)),
3763 sub_lo)),
3768 sub_lo)),
3779 sub_lo)),
3784 sub_lo)),
3789 sub_lo)),
3800 sub_lo))>;
3814 sub_lo)),
3824 sub_lo)),
3834 sub_lo)),
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/ |
| D | AVRInstPrinter.cpp | 94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); in getPrettyRegisterName()
|
| /external/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| D | AVRInstPrinter.cpp | 94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); in getPrettyRegisterName()
|
| /external/libvpx/libvpx/vp9/common/arm/neon/ |
| D | vp9_highbd_iht16x16_add_neon.c | 135 const int64x2x2_t sub_lo = vsubq_s64_dual(in0[0], in1[0]); in highbd_sub_dct_const_round_shift_low_8() local
139 out_lo.val[0] = vrshrn_n_s64(sub_lo.val[0], DCT_CONST_BITS); in highbd_sub_dct_const_round_shift_low_8()
140 out_lo.val[1] = vrshrn_n_s64(sub_lo.val[1], DCT_CONST_BITS); in highbd_sub_dct_const_round_shift_low_8()
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| D | vp9_highbd_iht8x8_add_neon.c | 81 const int64x2_t sub_lo = vsubq_s64(in0[0], in1[0]); in highbd_sub_dct_const_round_shift_low_8() local
83 const int32x2_t out_lo = vrshrn_n_s64(sub_lo, DCT_CONST_BITS); in highbd_sub_dct_const_round_shift_low_8()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 122 : AVR::sub_lo); in PrintAsmOperand()
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| D | AVRRegisterInfo.td | 31 def sub_lo : SubRegIndex<8>;
79 let SubRegIndices = [sub_lo, sub_hi],
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| D | AVRRegisterInfo.cpp | 275 LoReg = getSubReg(Reg, AVR::sub_lo); in splitReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 122 : AVR::sub_lo); in PrintAsmOperand()
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| D | AVRRegisterInfo.td | 31 def sub_lo : SubRegIndex<8>;
79 let SubRegIndices = [sub_lo, sub_hi],
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| D | AVRRegisterInfo.cpp | 272 LoReg = getSubReg(Reg, AVR::sub_lo); in splitReg()
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 32 def sub_lo : SubRegIndex<8>;
80 let SubRegIndices = [sub_lo, sub_hi],
|
| /external/llvm-project/llvm/test/CodeGen/Mips/msa/ |
| D | basic_operations_float.ll | 140 ; $w0:sub_lo
156 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
174 ; $w0:sub_lo
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| /external/llvm/test/CodeGen/Mips/msa/ |
| D | basic_operations_float.ll | 134 ; $w0:sub_lo
150 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
168 ; $w0:sub_lo
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 747 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi()
772 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
775 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
791 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64()
856 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
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| D | MipsRegisterInfo.td | 15 def sub_lo : SubRegIndex<32>;
55 let SubRegIndices = [sub_lo, sub_hi];
61 let SubRegIndices = [sub_lo, sub_hi];
74 let SubRegIndices = [sub_lo, sub_hi];
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| D | MipsSEFrameLowering.cpp | 210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC()
464 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); in emitPrologue()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 733 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi()
758 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
761 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
777 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64()
842 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
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| D | MipsRegisterInfo.td | 15 def sub_lo : SubRegIndex<32>;
55 let SubRegIndices = [sub_lo, sub_hi];
61 let SubRegIndices = [sub_lo, sub_hi];
74 let SubRegIndices = [sub_lo, sub_hi];
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| D | MipsSEFrameLowering.cpp | 210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC()
464 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); in emitPrologue()
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | fdct32x32_neon.c | 568 int32x4_t *add_lo, int32x4_t *add_hi, int32x4_t *sub_lo, in butterfly_one_coeff_s16_s32() argument
578 *sub_lo = vrshrq_n_s32(diff0, DCT_CONST_BITS); in butterfly_one_coeff_s16_s32()
594 int32x4_t *add_hi, int32x4_t *sub_lo, int32x4_t *sub_hi) { in butterfly_one_coeff_s32() argument
603 *sub_lo = vrshrq_n_s32(diff0, DCT_CONST_BITS); in butterfly_one_coeff_s32()
620 int32x4_t *add_lo, int32x4_t *add_hi, int32x4_t *sub_lo, in butterfly_two_coeff_s32() argument
632 *sub_lo = vrshrq_n_s32(diff0, DCT_CONST_BITS); in butterfly_two_coeff_s32()
|