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/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-vfloatintrinsics.ll15 %v4f16 = type <4 x half>
18 define %v4f16 @test_v4f16.sqrt(%v4f16 %a) {
29 %1 = call %v4f16 @llvm.sqrt.v4f16(%v4f16 %a)
30 ret %v4f16 %1
32 define %v4f16 @test_v4f16.powi(%v4f16 %a, i32 %b) {
36 %1 = call %v4f16 @llvm.powi.v4f16(%v4f16 %a, i32 %b)
37 ret %v4f16 %1
41 define %v4f16 @test_v4f16.sin(%v4f16 %a) {
47 %1 = call %v4f16 @llvm.sin.v4f16(%v4f16 %a)
48 ret %v4f16 %1
[all …]
Dfp16-vector-load-store.ll43 ; Load to one lane of v4f16
63 ; Simple store of v4f16
81 ; Store from one lane of v4f16
180 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
181 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
182 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
183 declare void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
184 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
185 declare void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <…
193 ; Load 2 x v4f16 with de-interleaving
[all …]
Dfp16_intrinsic_vector_2op.ll3 declare <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half>, <4 x half>)
5 declare <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half>, <4 x half>)
7 declare <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half>, <4 x half>)
9 declare <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half>, <4 x half>)
11 declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
37 %vmulx2.i = tail call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %b)
55 %vpminnm2.i = tail call <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half> %a, <4 x half> %b)
73 %vpmaxnm2.i = tail call <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half> %a, <4 x half> %b)
91 %vabdh_f16 = tail call <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half> %a, <4 x half> %b)
110 %abs = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %sub)
Dneon-fp16fml.ll3 declare <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
4 declare <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
5 declare <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
6 declare <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
16 …%vfmlal_low2.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %a, <4 x half> …
24 …%vfmlsl_low2.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %a, <4 x half> …
32 …%vfmlal_high2.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %a, <4 x half…
40 …%vfmlsl_high2.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %a, <4 x half…
Dfp16_intrinsic_vector_1op.ll3 declare <4 x half> @llvm.nearbyint.v4f16(<4 x half>)
5 declare <4 x half> @llvm.sqrt.v4f16(<4 x half>)
13 %vrndi1.i = tail call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %a)
31 %vsqrt.i = tail call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)
Dfp16-vector-nvcast.ll3 ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
14 ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
36 ; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
Dfp16_intrinsic_vector_3op.ll3 declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
11 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a)
Dneon-vcadd.ll8 …%vcadd_rot90_v2.i = tail call <4 x half> @llvm.aarch64.neon.vcadd.rot90.v4f16(<4 x half> %a, <4 x …
9 …%vcadd_rot270_v2.i = tail call <4 x half> @llvm.aarch64.neon.vcadd.rot270.v4f16(<4 x half> %a, <4 …
58 declare <4 x half> @llvm.aarch64.neon.vcadd.rot90.v4f16(<4 x half>, <4 x half>)
59 declare <4 x half> @llvm.aarch64.neon.vcadd.rot270.v4f16(<4 x half>, <4 x half>)
/external/llvm/test/CodeGen/AArch64/
Dfp16-vector-load-store.ll43 ; Load to one lane of v4f16
63 ; Simple store of v4f16
81 ; Store from one lane of v4f16
102 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
103 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
104 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
105 declare void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
106 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
107 declare void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <…
115 ; Load 2 x v4f16 with de-interleaving
[all …]
Dfp16-vector-nvcast.ll3 ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
14 ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
36 ; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.image.load.a16.d16.ll10 …%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i…
20 …%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i…
30 …%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i…
34 ; GCN-LABEL: {{^}}load.v4f16.1d:
37 define amdgpu_ps <4 x half> @load.v4f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
40 …%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, …
51 …%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, …
62 …%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, …
73 …%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, …
77 ; GCN-LABEL: {{^}}load.v4f16.2d:
[all …]
Dbitcast-v4f16-v4i16.ll3 ; creating v4i16->v4f16 and v4f16->v4i16 bitcasts in the selection DAG is rather
9 %a_tmp = call <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half> %1)
23 %a_half = call <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half> %a_half_tmp)
30 declare <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half>) #1
Dllvm.amdgcn.image.store.a16.d16.ll18 …call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, <8 x i32> %rsr…
35 …call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, <8 x i32> %rsr…
52 …call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, <8 x i32> %rsr…
69 …call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, <8 x i32> %rs…
87 …call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, <8 x i…
105 …call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, <8 x i…
123 …call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, <8 x i…
141 …call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, <8 x …
160 …call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, i16 %z…
179 …call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, i16 %z…
[all …]
Dllvm.amdgcn.image.d16.dim.ll46 …%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsr…
58 …%tex = call <4 x half> @llvm.amdgcn.image.load.mip.2d.v4f16.i32(i32 15, i32 %s, i32 %t, i32 %mip, …
137 …call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %data, i32 15, i32 %s, i32 %t, <8 x i32…
153 …call void @llvm.amdgcn.image.store.mip.1d.v4f16.i32(<4 x half> %data, i32 15, i32 %s, i32 %mip, <8…
160 declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
161 declare <4 x half> @llvm.amdgcn.image.load.mip.2d.v4f16.i32(i32, i32, i32, i32, <8 x i32>, i32, i32…
168 declare void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half>, i32, i32, i32, <8 x i32>, i32, i32) …
169 declare void @llvm.amdgcn.image.store.mip.1d.v4f16.i32(<4 x half>, i32, i32, i32, <8 x i32>, i32, i…
Dllvm.amdgcn.intersect_ray.ll4 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float4 ray_o…
6 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float4 ray_…
9 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <4 x float>, <4 x half…
11 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <4 x float>, <4 x half…
37 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_exten…
67 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_exten…
115 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_exten…
157 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_e…
Dllvm.amdgcn.image.gather4.d16.dim.ll14 …%tex = call <4 x half> @llvm.amdgcn.image.gather4.b.2d.v4f16.f32.f32(i32 4, float %bias, float %s,…
19 declare <4 x half> @llvm.amdgcn.image.gather4.b.2d.v4f16.f32.f32(i32, float, float, float, <8 x i32…
/external/llvm-project/llvm/test/CodeGen/ARM/
Darmv8.2a-fp16-vector-intrinsics.ll11 %vabs1.i = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)
201 %vcvta_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtas.v4i16.v4f16(<4 x half> %a)
210 %vcvta_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtau.v4i16.v4f16(<4 x half> %a)
228 %vcvtm_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtms.v4i16.v4f16(<4 x half> %a)
246 %vcvtm_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtmu.v4i16.v4f16(<4 x half> %a)
264 %vcvtn_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtns.v4i16.v4f16(<4 x half> %a)
282 %vcvtn_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtnu.v4i16.v4f16(<4 x half> %a)
300 %vcvtp_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtps.v4i16.v4f16(<4 x half> %a)
318 %vcvtp_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtpu.v4i16.v4f16(<4 x half> %a)
354 %vrecpe_v1.i = tail call <4 x half> @llvm.arm.neon.vrecpe.v4f16(<4 x half> %a)
[all …]
Dneon-vcadd.ll8 …%vcadd_rot90_v2.i = tail call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %a, <4 x half…
9 …%vcadd_rot270_v2.i = tail call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %a, <4 x ha…
47 declare <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half>, <4 x half>)
48 declare <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half>, <4 x half>)
Dfp16-intrinsic-vector-2op.ll4 declare <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half>, <4 x half>)
19 %vpadd_v2.i = tail call <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half> %a, <4 x half> %b)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h108 v4f16 = 53, // 4 x f16 enumerator
243 SimpleTy == MVT::v4f16 || SimpleTy == MVT::v2f32 || in is64BitVector()
357 case v4f16: in getVectorElementType()
408 case v4f16: in getVectorNumElements()
475 case v4f16: in getSizeInBits()
645 if (NumElements == 4) return MVT::v4f16; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
185 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
211 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
233 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.intersect_ray.ll5 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float4 ray_o…
7 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float4 ray_…
10 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <4 x float>, <4 x half…
12 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <4 x float>, <4 x half…
41 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_exten…
73 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_exten…
143 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_exten…
213 …%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_exten…
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2750 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2777 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2804 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2831 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2858 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2885 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2912 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2939 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2966 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2990 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1842 (VT != MVT::v4f32 || NarrowVT != MVT::v4f16)) in tryHighFPExt()
3188 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3215 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3242 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3269 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3296 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3323 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3350 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3377 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3404 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
[all …]

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