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Searched refs:v_lshlrev_b32_e32 (Results 1 – 25 of 208) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dload-local.128.ll49 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
50 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 24, v4
59 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
60 ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 24, v5
78 ; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
79 ; GFX9-NEXT: v_lshlrev_b32_e32 v7, 24, v7
87 ; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
88 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
109 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
113 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
[all …]
Dload-unaligned.ll33 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
37 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
41 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
47 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
51 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
55 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
68 ; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
72 ; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
78 ; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
81 ; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
[all …]
Dload-local.96.ll50 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
51 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 24, v4
60 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
61 ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 24, v5
75 ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
76 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 24, v2
97 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
101 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
108 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 24, v1
111 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
[all …]
Dinsertelement.i8.ll64 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
128 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
193 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
261 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
326 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
390 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
451 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
512 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
598 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 24, v4
606 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 24, v3
[all …]
Dextractelement.i8.ll45 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 24, v2
67 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v4
89 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
90 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
92 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
112 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v1
118 ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
138 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 24, v5
141 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v2
154 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
[all …]
Dshl.ll11 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
33 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 7, v0
104 ; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0
114 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 7, v0
143 ; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0
153 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 31, v0
200 ; GCN-NEXT: v_lshlrev_b32_e32 v0, s0, v0
211 ; GCN-NEXT: v_lshlrev_b32_e32 v0, v2, v0
212 ; GCN-NEXT: v_lshlrev_b32_e32 v1, v3, v1
222 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 31, v0
[all …]
Dllvm.amdgcn.image.load.2darraymsaa.a16.ll9 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
11 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v3
28 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
29 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
51 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
53 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v3
73 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
74 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
102 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
104 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v3
[all …]
Dload-constant.96.ll52 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v4
59 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 24, v5
61 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v8
62 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v7, 24, v9
64 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v8, 16, v12
65 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2
125 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v3
126 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 16, v4
127 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 24, v5
128 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 8, v7
[all …]
Dllvm.amdgcn.sdot4.ll51 ; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1
52 ; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v2
58 ; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v2
59 ; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v3
77 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
78 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
80 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v5
81 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v6
Dllvm.amdgcn.udot4.ll51 ; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1
52 ; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v2
58 ; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v2
59 ; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v3
77 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
78 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
80 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v5
81 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v6
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dload-local.128.ll90 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
92 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
96 ; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
97 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
101 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
103 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
115 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
117 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
121 ; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
124 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
[all …]
Dshl_add_ptr.ll19 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
36 ; GCN: v_lshlrev_b32_e32 [[OFS:v[0-9]+]], 2, {{v[0-9]+}}
78 ; GCN: v_lshlrev_b32_e32 [[OFS:v[0-9]+]], 2, {{v[0-9]+}}
101 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
131 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
146 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
160 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
174 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
188 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
202 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
[all …]
Dload-local.96.ll81 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
83 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
87 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
94 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
96 ; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
99 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
103 ; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
105 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
109 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
134 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
[all …]
Dshrink-add-sub-constant.ll16 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
30 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
47 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
58 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
81 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
99 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
120 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
135 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
166 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
180 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
[all …]
Dds-sub-offset.ll12 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
21 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
39 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
59 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
84 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
93 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
110 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
119 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
136 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
146 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
[all …]
Dshl.v2i16.ll71 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
83 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
107 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
122 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
144 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
156 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
180 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
191 ; CI-NEXT: v_lshlrev_b32_e32 v2, s8, v2
192 ; CI-NEXT: v_lshlrev_b32_e32 v3, s1, v3
194 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
[all …]
Dlshr.v2i16.ll71 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
83 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
107 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
123 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
144 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
156 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
180 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
194 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
213 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
225 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
[all …]
Dcallee-special-input-vgprs.ll152 ; VARABI: v_lshlrev_b32_e32 v0, 10, v1
155 ; FIXEDABI-DAG: v_lshlrev_b32_e32 [[TMP1:v[0-9]+]], 10, v1
156 ; FIXEDABI-DAG: v_lshlrev_b32_e32 [[TMP0:v[0-9]+]], 20, v2
175 ; VARABI: v_lshlrev_b32_e32 v0, 20, v2
179 ; FIXEDABI-DAG: v_lshlrev_b32_e32 [[TMP1:v[0-9]+]], 10, v1
180 ; FIXEDABI-DAG: v_lshlrev_b32_e32 [[TMP0:v[0-9]+]], 20, v2
193 ; VARABI: v_lshlrev_b32_e32 [[IDY:v[0-9]+]], 10, v1
198 ; FIXEDABI-DAG: v_lshlrev_b32_e32 [[TMP1:v[0-9]+]], 10, v1
199 ; FIXEDABI-DAG: v_lshlrev_b32_e32 [[TMP0:v[0-9]+]], 20, v2
212 ; VARABI: v_lshlrev_b32_e32 [[IDZ:v[0-9]+]], 20, v2
[all …]
Dshift-i64-opts.ll73 ; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 3, [[VAL]]
96 ; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 31, [[VAL]]
126 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 31, [[VAL]]
138 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
150 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
162 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 7, [[VAL]]
174 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]
187 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]
199 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[VAL]]
222 ; GCN-DAG: v_lshlrev_b32_e32 v[[RESHI:[0-9]+]], 16, v{{[0-9]+}}
[all …]
Dds_read2.ll15 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
29 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
51 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
65 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
87 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
102 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
125 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
142 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
181 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
200 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
[all …]
/external/llvm-project/llvm/test/Object/AMDGPU/
Dobjdump.s20 v_lshlrev_b32_e32 v4, 2, v0
44 v_lshlrev_b32_e32 v6, 5, v8
45 v_lshlrev_b32_e32 v7, 2, v7
/external/llvm/test/Object/AMDGPU/
Dobjdump.s18 v_lshlrev_b32_e32 v4, 2, v0
40 v_lshlrev_b32_e32 v6, 5, v8
41 v_lshlrev_b32_e32 v7, 2, v7
/external/llvm/test/CodeGen/AMDGPU/
Dds-sub-offset.ll8 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0
23 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
38 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
53 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
75 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
95 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
109 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
Dshl_add_ptr.ll19 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
36 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
72 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
89 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
119 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
134 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
148 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
162 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
176 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
190 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
[all …]
Dshift-i64-opts.ll73 ; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 3, [[VAL]]
96 ; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 31, [[VAL]]
126 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 31, [[VAL]]
138 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
150 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
162 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 7, [[VAL]]
174 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]
187 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]
199 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[VAL]]
222 ; GCN-DAG: v_lshlrev_b32_e32 v[[RESHI:[0-9]+]], 16, v{{[0-9]+}}
[all …]

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