1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX906 %s
3; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
5
6define i32 @v_sdot4(i32 %a, i32 %b, i32 %c) {
7; GFX906-LABEL: v_sdot4:
8; GFX906:       ; %bb.0:
9; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
11; GFX906-NEXT:    s_setpc_b64 s[30:31]
12;
13; GFX10-LABEL: v_sdot4:
14; GFX10:       ; %bb.0:
15; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
17; GFX10-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
18; GFX10-NEXT:    s_setpc_b64 s[30:31]
19  %r = call i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 false)
20  ret i32 %r
21}
22
23define i32 @v_sdot4_clamp(i32 %a, i32 %b, i32 %c) {
24; GFX906-LABEL: v_sdot4_clamp:
25; GFX906:       ; %bb.0:
26; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2 clamp
28; GFX906-NEXT:    s_setpc_b64 s[30:31]
29;
30; GFX10-LABEL: v_sdot4_clamp:
31; GFX10:       ; %bb.0:
32; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
34; GFX10-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2 clamp
35; GFX10-NEXT:    s_setpc_b64 s[30:31]
36  %r = call i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 true)
37  ret i32 %r
38}
39
40; FIXME: bitcast should not expand
41define i32 @v_sdot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) {
42; GFX906-LABEL: v_sdot4_cast_v4i8:
43; GFX906:       ; %bb.0:
44; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45; GFX906-NEXT:    s_mov_b32 s5, 8
46; GFX906-NEXT:    s_movk_i32 s4, 0xff
47; GFX906-NEXT:    v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
48; GFX906-NEXT:    v_and_or_b32 v0, v0, s4, v1
49; GFX906-NEXT:    v_and_b32_e32 v1, s4, v2
50; GFX906-NEXT:    v_and_b32_e32 v2, s4, v3
51; GFX906-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
52; GFX906-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
53; GFX906-NEXT:    v_or3_b32 v0, v0, v1, v2
54; GFX906-NEXT:    v_lshlrev_b32_sdwa v1, s5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
55; GFX906-NEXT:    v_and_b32_e32 v2, s4, v6
56; GFX906-NEXT:    v_and_b32_e32 v3, s4, v7
57; GFX906-NEXT:    v_and_or_b32 v1, v4, s4, v1
58; GFX906-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
59; GFX906-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
60; GFX906-NEXT:    v_or3_b32 v1, v1, v2, v3
61; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v8
62; GFX906-NEXT:    s_setpc_b64 s[30:31]
63;
64; GFX10-LABEL: v_sdot4_cast_v4i8:
65; GFX10:       ; %bb.0:
66; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
67; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
68; GFX10-NEXT:    s_mov_b32 s4, 8
69; GFX10-NEXT:    s_movk_i32 s5, 0xff
70; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
71; GFX10-NEXT:    v_and_or_b32 v0, v0, s5, v1
72; GFX10-NEXT:    v_and_b32_e32 v1, s5, v2
73; GFX10-NEXT:    v_and_b32_e32 v2, s5, v3
74; GFX10-NEXT:    v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
75; GFX10-NEXT:    v_and_b32_e32 v5, s5, v6
76; GFX10-NEXT:    v_and_b32_e32 v6, s5, v7
77; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
78; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
79; GFX10-NEXT:    v_and_or_b32 v3, v4, s5, v3
80; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v5
81; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 24, v6
82; GFX10-NEXT:    v_or3_b32 v7, v0, v1, v2
83; GFX10-NEXT:    v_or3_b32 v1, v3, v4, v5
84; GFX10-NEXT:    v_dot4_i32_i8 v0, v7, v1, v8
85; GFX10-NEXT:    s_setpc_b64 s[30:31]
86  %a.cast = bitcast <4 x i8> %a to i32
87  %b.cast = bitcast <4 x i8> %b to i32
88  %r = call i32 @llvm.amdgcn.sdot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)
89  ret i32 %r
90}
91
92define i32 @v_sdot4_fnegf32_a(float %a, i32 %b, i32 %c) {
93; GFX906-LABEL: v_sdot4_fnegf32_a:
94; GFX906:       ; %bb.0:
95; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
96; GFX906-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
97; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
98; GFX906-NEXT:    s_setpc_b64 s[30:31]
99;
100; GFX10-LABEL: v_sdot4_fnegf32_a:
101; GFX10:       ; %bb.0:
102; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
103; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
104; GFX10-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
105; GFX10-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
106; GFX10-NEXT:    s_setpc_b64 s[30:31]
107  %neg.a = fneg float %a
108  %cast.neg.a = bitcast float %neg.a to i32
109  %r = call i32 @llvm.amdgcn.sdot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
110  ret i32 %r
111}
112
113define i32 @v_sdot4_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {
114; GFX906-LABEL: v_sdot4_fnegv2f16_a:
115; GFX906:       ; %bb.0:
116; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
117; GFX906-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
118; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
119; GFX906-NEXT:    s_setpc_b64 s[30:31]
120;
121; GFX10-LABEL: v_sdot4_fnegv2f16_a:
122; GFX10:       ; %bb.0:
123; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
124; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
125; GFX10-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
126; GFX10-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
127; GFX10-NEXT:    s_setpc_b64 s[30:31]
128  %neg.a = fneg <2 x half> %a
129  %cast.neg.a = bitcast <2 x half> %neg.a to i32
130  %r = call i32 @llvm.amdgcn.sdot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
131  ret i32 %r
132}
133
134declare i32 @llvm.amdgcn.sdot4(i32, i32, i32, i1 immarg) #0
135
136attributes #0 = { nounwind readnone speculatable }
137