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Searched refs:v_lshrrev_b32_e32 (Results 1 – 25 of 136) sorted by relevance

123456

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dextractelement.i8.ll41 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
42 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 24, v0
49 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0
62 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
64 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 24, v0
70 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0
83 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v0
84 ; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
86 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v0
96 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0
[all …]
Dinsertelement.i8.ll14 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v1
34 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 8, v0
58 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v1
81 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
99 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 8, v0
122 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v0
145 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v1
164 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 8, v1
187 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v1
211 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v2
[all …]
Dload-unaligned.ll181 ; GFX7-NEXT: v_lshrrev_b32_e32 v5, 8, v1
182 ; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v1
183 ; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v1
188 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v2
189 ; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v2
190 ; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2
195 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v3
196 ; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v3
197 ; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v3
202 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v4
[all …]
Dlshr.ll13 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
36 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 7, v0
102 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
113 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 7, v0
145 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
155 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
202 ; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0
213 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0
214 ; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1
224 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
[all …]
Dextractelement.i16.ll33 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0
46 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0
59 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0
72 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v2
78 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0
85 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v2
91 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0
98 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 1, v2
104 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0
115 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v0
[all …]
Dfma.ll98 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
99 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
100 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
125 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
142 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
143 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
144 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
170 ; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
187 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
188 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
[all …]
Dcvt_f32_ubyte.ll48 ; SI-NEXT: v_lshrrev_b32_e32 v0, 7, v0
56 ; VI-NEXT: v_lshrrev_b32_e32 v0, 7, v0
69 ; SI-NEXT: v_lshrrev_b32_e32 v0, 8, v0
77 ; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v0
90 ; SI-NEXT: v_lshrrev_b32_e32 v0, 8, v0
103 ; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v0
119 ; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
170 ; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
181 ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
194 ; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
[all …]
Dload-constant.96.ll308 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v6
309 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v7
310 ; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v8
325 ; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v0
326 ; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v0
327 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0
328 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
329 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
330 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
332 ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v2
[all …]
Dllvm.amdgcn.intersect_ray.ll29 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v6
31 ; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
61 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v7
63 ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
112 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v6
114 ; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
182 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v7
184 ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dstrict_fma.f16.ll25 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
26 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2
27 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
48 ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
49 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v4
50 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
65 ; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v1
66 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v5
67 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3
69 ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0
[all …]
Dstore-hi16.ll11 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
31 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
51 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
70 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
90 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
110 ; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
113 ; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
134 ; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
137 ; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
157 ; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
[all …]
Dllvm.fma.f16.ll110 ; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
111 ; SI: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
112 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
126 ; VI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
127 ; VI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
128 ; VI: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
163 ; SIVI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
164 ; SIVI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
209 ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
211 ; SI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
[all …]
Dfmin_legacy.f16.ll67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
68 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
87 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
142 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
143 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
165 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
233 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
234 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
[all …]
Dfmax_legacy.f16.ll66 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
85 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
141 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
142 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
163 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
232 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
233 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
[all …]
Dextract-load-i1.ll18 ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 4, v0
20 ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 6, v0
21 ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 7, v0
Dpartial-shift-shrink.ll8 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
28 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 15, v0
40 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
80 ; GCN-DAG: v_lshrrev_b32_e32 v0, 16, v0
107 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
Dsdwa-peephole.ll7 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
24 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
40 ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
41 ; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}}
74 ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
75 ; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}}
97 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
98 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
124 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
125 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
[all …]
Dselect.f16.ll443 ; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
445 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
449 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
450 ; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
497 ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
500 ; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
503 ; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
504 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
553 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
555 ; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
[all …]
Dload-global-i16.ll1155 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
1170 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v2
1189 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
1354 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
1372 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v3
1394 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
1584 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
1585 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
1602 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v5
1603 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v4
[all …]
Dsrl.ll8 ; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
24 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
25 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
45 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
46 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
47 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
Dshift-and-i128-ubfe.ll10 ; GCN: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
33 ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
55 ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
78 ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
98 ; GCN-DAG: v_lshrrev_b32_e32 v[[ELT1PART:[0-9]+]], 2, v{{[[0-9]+}}
Dlshr.v2i16.ll116 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
118 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
190 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
192 ; CI-NEXT: v_lshrrev_b32_e32 v3, s1, v3
193 ; CI-NEXT: v_lshrrev_b32_e32 v2, s8, v2
259 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
321 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
364 ; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v0
382 ; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2
449 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
[all …]
Dllvm.fmuladd.f16.ll137 ; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
138 ; SI: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
139 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
154 ; VI-FLUSH: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
161 ; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
162 ; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
163 ; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
/external/llvm/test/CodeGen/AMDGPU/
Dsrl.ll8 ; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
24 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
25 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
45 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
46 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
47 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
Dshift-and-i128-ubfe.ll10 ; GCN: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
32 ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
54 ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
76 ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
96 ; GCN-DAG: v_lshrrev_b32_e32 v[[ELT1PART:[0-9]+]], 2, v{{[[0-9]+}}

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