1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI -check-prefix=SI-FLUSH %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s 3; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI -check-prefix=SI-DENORM %s 4; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s 5; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX10 -check-prefix=GFX10-FLUSH %s 6; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX10 -check-prefix=GFX10-DENORM %s 7 8declare half @llvm.fmuladd.f16(half %a, half %b, half %c) 9declare <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) 10 11; GCN-LABEL: {{^}}fmuladd_f16 12; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 13; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 14; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] 15; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 16; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 17; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]] 18; SI: v_mac_f32_e32 v[[C_F32]], v[[A_F32]], v[[B_F32]] 19; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]] 20; SI: buffer_store_short v[[R_F16]] 21 22; VI-FLUSH: v_mac_f16_e32 v[[C_F16]], v[[A_F16]], v[[B_F16]] 23; VI-FLUSH: buffer_store_short v[[C_F16]] 24 25; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] 26; VI-DENORM: buffer_store_short [[RESULT]] 27 28; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], v[[A_F16]], v[[B_F16]] 29; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]] 30; GFX10-FLUSH: buffer_store_short [[ADD]] 31 32; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], v[[A_F16]], v[[B_F16]] 33; GFX10-DENORM: buffer_store_short v[[C_F16]], 34 35; GCN: s_endpgm 36define amdgpu_kernel void @fmuladd_f16( 37 half addrspace(1)* %r, 38 half addrspace(1)* %a, 39 half addrspace(1)* %b, 40 half addrspace(1)* %c) { 41 %a.val = load half, half addrspace(1)* %a 42 %b.val = load half, half addrspace(1)* %b 43 %c.val = load half, half addrspace(1)* %c 44 %r.val = call half @llvm.fmuladd.f16(half %a.val, half %b.val, half %c.val) 45 store half %r.val, half addrspace(1)* %r 46 ret void 47} 48 49; GCN-LABEL: {{^}}fmuladd_f16_imm_a 50; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 51; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] 52; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 53; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]] 54; SI: v_mac_f32_e32 v[[C_F32]], 0x40400000, v[[B_F32]] 55; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]] 56; SI: buffer_store_short v[[R_F16]] 57 58; VI-FLUSH: v_mac_f16_e32 v[[C_F16]], 0x4200, v[[B_F16]] 59; VI-FLUSH: buffer_store_short v[[C_F16]] 60 61; VI-DENORM: s_movk_i32 [[KA:s[0-9]+]], 0x4200 62; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[B_F16]], [[KA]], v[[C_F16]] 63; VI-DENORM: buffer_store_short [[RESULT]] 64 65; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x4200, v[[B_F16]] 66; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]] 67; GFX10-FLUSH: buffer_store_short [[ADD]] 68 69; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], 0x4200, v[[B_F16]] 70; GFX10-DENORM: buffer_store_short v[[C_F16]], 71 72; GCN: s_endpgm 73define amdgpu_kernel void @fmuladd_f16_imm_a( 74 half addrspace(1)* %r, 75 half addrspace(1)* %b, 76 half addrspace(1)* %c) { 77 %b.val = load volatile half, half addrspace(1)* %b 78 %c.val = load volatile half, half addrspace(1)* %c 79 %r.val = call half @llvm.fmuladd.f16(half 3.0, half %b.val, half %c.val) 80 store half %r.val, half addrspace(1)* %r 81 ret void 82} 83 84; GCN-LABEL: {{^}}fmuladd_f16_imm_b 85; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 86; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] 87; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 88; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]] 89; SI: v_mac_f32_e32 v[[C_F32]], 0x40400000, v[[A_F32]] 90; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]] 91; SI: buffer_store_short v[[R_F16]] 92 93; VI-FLUSH: v_mac_f16_e32 v[[C_F16]], 0x4200, v[[A_F16]] 94; VI-FLUSH: buffer_store_short v[[C_F16]] 95 96; VI-DENORM: s_movk_i32 [[KA:s[0-9]+]], 0x4200 97; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[A_F16]], [[KA]], v[[C_F16]] 98; VI-DENORM: buffer_store_short [[RESULT]] 99 100; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x4200, v[[A_F16]] 101; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]] 102; GFX10-FLUSH: buffer_store_short [[ADD]] 103 104; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], 0x4200, v[[A_F16]] 105; GFX10-DENORM: buffer_store_short v[[C_F16]], 106 107; GCN: s_endpgm 108define amdgpu_kernel void @fmuladd_f16_imm_b( 109 half addrspace(1)* %r, 110 half addrspace(1)* %a, 111 half addrspace(1)* %c) { 112 %a.val = load volatile half, half addrspace(1)* %a 113 %c.val = load volatile half, half addrspace(1)* %c 114 %r.val = call half @llvm.fmuladd.f16(half %a.val, half 3.0, half %c.val) 115 store half %r.val, half addrspace(1)* %r 116 ret void 117} 118 119; GCN-LABEL: {{^}}fmuladd_v2f16 120; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]] 121; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]] 122; SI: buffer_load_dword v[[C_V2_F16:[0-9]+]] 123 124; VI-FLUSH: buffer_load_dword v[[A_V2_F16:[0-9]+]] 125; VI-FLUSH: buffer_load_dword v[[C_V2_F16:[0-9]+]] 126; VI-FLUSH: buffer_load_dword v[[B_V2_F16:[0-9]+]] 127 128; VI-DENORM: buffer_load_dword v[[A_V2_F16:[0-9]+]] 129; VI-DENORM: buffer_load_dword v[[B_V2_F16:[0-9]+]] 130; VI-DENORM: buffer_load_dword v[[C_V2_F16:[0-9]+]] 131 132; GFX10: buffer_load_dword v[[A_V2_F16:[0-9]+]] 133; GFX10: buffer_load_dword v[[B_V2_F16:[0-9]+]] 134; GFX10: buffer_load_dword v[[C_V2_F16:[0-9]+]] 135 136; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 137; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 138; SI: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]] 139; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 140 141; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] 142; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V2_F16]] 143 144; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 145; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] 146; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_1:[0-9]+]], v[[C_F16_1]] 147; SI-DAG: v_mac_f32_e32 v[[C_F32_0]], v[[A_F32_0]], v[[B_F32_0]] 148; SI-DAG: v_mac_f32_e32 v[[C_F32_1]], v[[A_F32_1]], v[[B_F32_1]] 149; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[C_F32_1]] 150; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_LO:[0-9]+]], v[[C_F32_0]] 151; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 152; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_LO]], v[[R_F16_HI]] 153 154; VI-FLUSH: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]] 155; VI-FLUSH-DAG: v_mac_f16_sdwa v[[C_F16_1]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 156; VI-FLUSH-DAG: v_mac_f16_e32 v[[C_V2_F16]], v[[A_V2_F16]], v[[B_V2_F16]] 157; VI-FLUSH-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[C_F16_1]] 158; VI-FLUSH-NOT: v_and_b32 159; VI-FLUSH: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[C_V2_F16]], v[[R_F16_HI]] 160 161; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 162; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 163; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]] 164; VI-DENORM-DAG: v_fma_f16 v[[RES0:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]], v[[C_V2_F16]] 165; VI-DENORM-DAG: v_fma_f16 v[[RES1:[0-9]+]], v[[A_F16_1]], v[[B_F16_1]], v[[C_F16_1]] 166; VI-DENORM-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[RES1]] 167; VI-DENORM-NOT: v_and_b32 168; VI-DENORM: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[RES0]], v[[R_F16_HI]] 169 170; GFX10-FLUSH: v_pk_mul_f16 [[MUL:v[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] 171; GFX10-FLUSH: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], [[MUL]], v[[C_V2_F16]] 172 173; GFX10-DENORM: v_pk_fma_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]], v[[C_V2_F16]] 174 175; GCN: buffer_store_dword v[[R_V2_F16]] 176define amdgpu_kernel void @fmuladd_v2f16( 177 <2 x half> addrspace(1)* %r, 178 <2 x half> addrspace(1)* %a, 179 <2 x half> addrspace(1)* %b, 180 <2 x half> addrspace(1)* %c) { 181 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 182 %b.val = load <2 x half>, <2 x half> addrspace(1)* %b 183 %c.val = load <2 x half>, <2 x half> addrspace(1)* %c 184 %r.val = call <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a.val, <2 x half> %b.val, <2 x half> %c.val) 185 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 186 ret void 187} 188