| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | regbankselect-extract-vector-elt.mir | 47 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
48 …vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:…
51 ; WAVE64: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV]]
54 ; WAVE64: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[UV2]], [[SELECT]]
57 ; WAVE64: [[SELECT2:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP2]](s1), [[UV3]], [[SELECT1]]
60 ; WAVE64: [[SELECT3:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP3]](s1), [[UV4]], [[SELECT2]]
63 ; WAVE64: [[SELECT4:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP4]](s1), [[UV5]], [[SELECT3]]
66 ; WAVE64: [[SELECT5:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP5]](s1), [[UV6]], [[SELECT4]]
69 ; WAVE64: [[SELECT6:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP6]](s1), [[UV7]], [[SELECT5]]
72 ; WAVE64: [[SELECT7:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP7]](s1), [[UV8]], [[SELECT6]]
[all …]
|
| D | regbankselect-insert-vector-elt.mir | 48 ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
49 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $sgpr0
51 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
52 …; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0…
55 ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY1]], [[UV]]
58 ; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[COPY1]], [[UV1]]
61 ; CHECK: [[SELECT2:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP2]](s1), [[COPY1]], [[UV2]]
64 ; CHECK: [[SELECT3:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP3]](s1), [[COPY1]], [[UV3]]
65 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s3…
84 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
[all …]
|
| D | regbankselect-select.mir | 47 ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
51 ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
52 ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY3]]
57 ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
61 ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
62 ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY3]]
82 ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
86 ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
87 ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY3]], [[COPY5]]
92 ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
[all …]
|
| D | regbankselect-and.mir | 30 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
31 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
32 ; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY2]], [[COPY1]]
46 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
48 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
49 ; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[COPY2]]
63 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
64 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
65 ; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[COPY1]]
96 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
[all …]
|
| D | regbankselect-or.mir | 30 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
31 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
32 ; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY2]], [[COPY1]]
46 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
48 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
49 ; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY]], [[COPY2]]
63 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
64 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
65 ; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY]], [[COPY1]]
108 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
[all …]
|
| D | inst-select-fadd.s16.mir | 18 %0:vgpr(s32) = COPY $vgpr0
19 %1:vgpr(s32) = COPY $vgpr1
20 %2:vgpr(s16) = G_TRUNC %0
21 %3:vgpr(s16) = G_TRUNC %1
22 %4:vgpr(s16) = G_FADD %2, %3
42 %1:vgpr(s32) = COPY $vgpr0
44 %3:vgpr(s16) = G_TRUNC %1
45 %4:vgpr(s16) = G_FADD %2, %3
64 %0:vgpr(s32) = COPY $vgpr0
66 %2:vgpr(s16) = G_TRUNC %0
[all …]
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| D | inst-select-icmp.mir | 32 %0:vgpr(p1) = COPY $vgpr0_vgpr1
45 %13:vgpr(s32) = COPY %11
47 %14:vgpr(s32) = COPY %12
72 %0:vgpr(p1) = COPY $vgpr0_vgpr1
97 %25:vgpr(s32) = COPY %15
99 %26:vgpr(s32) = COPY %16
101 %27:vgpr(s32) = COPY %17
103 %28:vgpr(s32) = COPY %18
105 %29:vgpr(s32) = COPY %19
107 %30:vgpr(s32) = COPY %20
[all …]
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| D | inst-select-ashr.s16.mir | 14 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:vgpr, %1:vgpr(s32) (in f…
15 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %5:vgpr(s64) = G_ZEXT %4:vgpr(s16) (in function: …
17 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:sgpr, %1:vgpr(s32) (in f…
18 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:vgpr, %1:sgpr(s32) (in f…
82 %0:vgpr(s32) = COPY $vgpr0
84 %2:vgpr(s16) = G_TRUNC %0
86 %4:vgpr(s16) = G_ASHR %2, %3
100 ; GFX8: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
101 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
102 ; GFX8: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
[all …]
|
| D | inst-select-lshr.s16.mir | 14 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_LSHR %2:vgpr, %1:vgpr(s32) (in f…
15 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %5:vgpr(s64) = G_ZEXT %4:vgpr(s16) (in function: …
17 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_LSHR %2:sgpr, %1:vgpr(s32) (in f…
18 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_LSHR %2:vgpr, %1:sgpr(s32) (in f…
82 %0:vgpr(s32) = COPY $vgpr0
84 %2:vgpr(s16) = G_TRUNC %0
86 %4:vgpr(s16) = G_LSHR %2, %3
100 ; GFX8: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
101 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
102 ; GFX8: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
[all …]
|
| D | inst-select-shl.s16.mir | 14 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:vgpr, %1:vgpr(s32) (in fu…
15 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %5:vgpr(s64) = G_ZEXT %4:vgpr(s16) (in function: …
17 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:sgpr, %1:vgpr(s32) (in fu…
18 # ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:vgpr, %1:sgpr(s32) (in fu…
82 %0:vgpr(s32) = COPY $vgpr0
84 %2:vgpr(s16) = G_TRUNC %0
86 %4:vgpr(s16) = G_SHL %2, %3
100 ; GFX8: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
101 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
102 ; GFX8: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
[all …]
|
| D | regbankselect-xor.mir | 30 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
31 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
32 ; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY2]], [[COPY1]]
46 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
48 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
49 ; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY2]]
63 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
64 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
65 ; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY1]]
108 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
[all …]
|
| D | inst-select-store-atomic-local.mir | 34 %0:vgpr(s32) = COPY $vgpr0
35 %1:vgpr(p3) = COPY $vgpr1
53 ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
54 ; GFX6: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
59 ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
60 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
65 ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
66 ; GFX9: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
68 %0:vgpr(<2 x s16>) = COPY $vgpr0
69 %1:vgpr(p3) = COPY $vgpr1
[all …]
|
| D | inst-select-fcmp.s16.mir | 14 ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
15 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
16 ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
17 ; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
21 ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
22 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
23 ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
24 ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
27 %0:vgpr(s32) = COPY $vgpr0
28 %1:vgpr(s32) = COPY $vgpr1
[all …]
|
| D | inst-select-store-atomic-flat.mir | 26 %0:vgpr(s32) = COPY $vgpr0
27 %1:vgpr(p0) = COPY $vgpr1_vgpr2
45 ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
46 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(p0) = COPY $vgpr1_vgpr2
50 ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
51 ; GFX9: [[COPY1:%[0-9]+]]:vgpr(p0) = COPY $vgpr1_vgpr2
53 %0:vgpr(<2 x s16>) = COPY $vgpr0
54 %1:vgpr(p0) = COPY $vgpr1_vgpr2
72 ; GFX7: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
73 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(p0) = COPY $vgpr1_vgpr2
[all …]
|
| D | regbankselect-sext-inreg.mir | 104 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
105 ; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY]], 1
122 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
123 ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
124 ; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 1
125 ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
126 ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
127 ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
144 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
145 ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
[all …]
|
| D | inst-select-pattern-smed3.s16.mir | 29 %0:vgpr(s32) = COPY $vgpr0
30 %1:vgpr(s32) = COPY $vgpr1
31 %2:vgpr(s32) = COPY $vgpr2
32 %3:vgpr(s16) = G_TRUNC %0
33 %4:vgpr(s16) = G_TRUNC %1
34 %5:vgpr(s16) = G_TRUNC %2
36 %6:vgpr(s16) = G_SMAX %3, %4
37 %7:vgpr(s16) = G_SMIN %3, %4
38 %8:vgpr(s16) = G_SMAX %7, %5
39 %9:vgpr(s16) = G_SMIN %6, %8
[all …]
|
| D | inst-select-pattern-umed3.s16.mir | 29 %0:vgpr(s32) = COPY $vgpr0
30 %1:vgpr(s32) = COPY $vgpr1
31 %2:vgpr(s32) = COPY $vgpr2
32 %3:vgpr(s16) = G_TRUNC %0
33 %4:vgpr(s16) = G_TRUNC %1
34 %5:vgpr(s16) = G_TRUNC %2
36 %6:vgpr(s16) = G_UMAX %3, %4
37 %7:vgpr(s16) = G_UMIN %3, %4
38 %8:vgpr(s16) = G_UMAX %7, %5
39 %9:vgpr(s16) = G_UMIN %6, %8
[all …]
|
| D | regbankselect-amdgcn.s.buffer.load.ll | 17 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32)
31 ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32)
51 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
54 ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
69 ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
72 ; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
97 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
100 ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
103 ; CHECK: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32)
123 ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
[all …]
|
| D | regbankselect-fma.mir | 16 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
17 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
19 ; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY3]], [[COPY4]], [[COPY5]]
33 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
36 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
38 ; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY3]], [[COPY4]]
53 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
55 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
[all …]
|
| D | regbankselect-fshr.mir | 16 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
17 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
19 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY4]], [[COPY5]](s32)
33 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
36 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
38 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY3]], [[COPY4]](s32)
53 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
55 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
[all …]
|
| D | inst-select-fmul.v2s16.mir | 18 %0:vgpr(<2 x s16>) = COPY $vgpr0
19 %1:vgpr(<2 x s16>) = COPY $vgpr1
20 %2:vgpr(<2 x s16>) = G_FMUL %0, %1
38 %0:vgpr(<2 x s16>) = COPY $vgpr0
39 %1:vgpr(<2 x s16>) = COPY $vgpr1
40 %2:vgpr(<2 x s16>) = G_FNEG %0
41 %3:vgpr(<2 x s16>) = G_FNEG %1
42 %4:vgpr(<2 x s16>) = G_FMUL %2, %3
57 ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
58 ; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
[all …]
|
| D | inst-select-fadd.s64.mir | 18 %0:vgpr(s64) = COPY $vgpr0_vgpr1
19 %1:vgpr(s64) = COPY $vgpr2_vgpr3
20 %2:vgpr(s64) = G_FADD %0, %1
40 %1:vgpr(s64) = COPY $vgpr0_vgpr1
41 %2:vgpr(s64) = G_FADD %0, %1
60 %0:vgpr(s64) = COPY $vgpr0_vgpr1
62 %2:vgpr(s64) = G_FADD %0, %1
81 %0:vgpr(s64) = COPY $vgpr0_vgpr1
82 %1:vgpr(s64) = COPY $vgpr2_vgpr3
83 %2:vgpr(s64) = G_FABS %0
[all …]
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| D | inst-select-fadd.s32.mir | 18 %0:vgpr(s32) = COPY $vgpr0
19 %1:vgpr(s32) = COPY $vgpr1
20 %2:vgpr(s32) = G_FADD %0, %1
40 %1:vgpr(s32) = COPY $vgpr0
41 %2:vgpr(s32) = G_FADD %0, %1
60 %0:vgpr(s32) = COPY $vgpr0
62 %2:vgpr(s32) = G_FADD %0, %1
81 %0:vgpr(s32) = COPY $vgpr0
82 %1:vgpr(s32) = COPY $vgpr1
83 %2:vgpr(s32) = G_FABS %0
[all …]
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| D | inst-select-fmul.mir | 25 %1:vgpr(s32) = COPY $vgpr0
26 %2:vgpr(s32) = COPY $vgpr1
27 %3:vgpr(p1) = COPY $vgpr3_vgpr4
30 %4:vgpr(s32) = G_FMUL %1, %0
33 %5:vgpr(s32) = G_FMUL %0, %1
36 %6:vgpr(s32) = G_FMUL %1, %2
61 %1:vgpr(s64) = COPY $vgpr0_vgpr1
62 %2:vgpr(s64) = COPY $vgpr2_vgpr3
63 %3:vgpr(p1) = COPY $vgpr4_vgpr5
66 %4:vgpr(s64) = G_FMUL %1, %0
[all …]
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| D | inst-select-pattern-umed3.mir | 19 %0:vgpr(s32) = COPY $vgpr0
20 %1:vgpr(s32) = COPY $vgpr1
21 %2:vgpr(s32) = COPY $vgpr2
22 %3:vgpr(s32) = G_UMAX %0, %1
23 %4:vgpr(s32) = G_UMIN %0, %1
24 %5:vgpr(s32) = G_UMAX %4, %2
25 %6:vgpr(s32) = G_UMIN %3, %5
76 %0:vgpr(s32) = COPY $vgpr0
77 %1:vgpr(s32) = COPY $vgpr1
78 %2:vgpr(s32) = COPY $vgpr2
[all …]
|