1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s 3 4--- 5 6name: fadd_s32_vvv 7legalized: true 8regBankSelected: true 9 10body: | 11 bb.0: 12 liveins: $vgpr0, $vgpr1 13 ; GFX6-LABEL: name: fadd_s32_vvv 14 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 15 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 16 ; GFX6: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 17 ; GFX6: S_ENDPGM 0, implicit %2 18 %0:vgpr(s32) = COPY $vgpr0 19 %1:vgpr(s32) = COPY $vgpr1 20 %2:vgpr(s32) = G_FADD %0, %1 21 S_ENDPGM 0, implicit %2 22 23... 24 25--- 26 27name: fadd_s32_vsv 28legalized: true 29regBankSelected: true 30 31body: | 32 bb.0: 33 liveins: $vgpr0, $sgpr0 34 ; GFX6-LABEL: name: fadd_s32_vsv 35 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 36 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 37 ; GFX6: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 38 ; GFX6: S_ENDPGM 0, implicit %2 39 %0:sgpr(s32) = COPY $sgpr0 40 %1:vgpr(s32) = COPY $vgpr0 41 %2:vgpr(s32) = G_FADD %0, %1 42 S_ENDPGM 0, implicit %2 43 44... 45 46--- 47 48name: fadd_s32_vvs 49legalized: true 50regBankSelected: true 51 52body: | 53 bb.0: 54 liveins: $vgpr0, $sgpr0 55 ; GFX6-LABEL: name: fadd_s32_vvs 56 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 57 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 58 ; GFX6: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 59 ; GFX6: S_ENDPGM 0, implicit %2 60 %0:vgpr(s32) = COPY $vgpr0 61 %1:sgpr(s32) = COPY $sgpr0 62 %2:vgpr(s32) = G_FADD %0, %1 63 S_ENDPGM 0, implicit %2 64 65... 66 67--- 68 69name: fadd_s32_vvv_fabs_lhs 70legalized: true 71regBankSelected: true 72 73body: | 74 bb.0: 75 liveins: $vgpr0, $vgpr1 76 ; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs 77 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 78 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 79 ; GFX6: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 80 ; GFX6: S_ENDPGM 0, implicit %3 81 %0:vgpr(s32) = COPY $vgpr0 82 %1:vgpr(s32) = COPY $vgpr1 83 %2:vgpr(s32) = G_FABS %0 84 %3:vgpr(s32) = G_FADD %2, %1 85 S_ENDPGM 0, implicit %3 86 87... 88 89--- 90 91name: fadd_s32_vvv_fabs_rhs 92legalized: true 93regBankSelected: true 94 95body: | 96 bb.0: 97 liveins: $vgpr0, $vgpr1 98 ; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs 99 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 100 ; GFX6: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec 101 ; GFX6: S_ENDPGM 0, implicit %3 102 %0:vgpr(s32) = COPY $vgpr0 103 %1:vgpr(s32) = COPY $vgpr1 104 %2:vgpr(s32) = G_FABS %1 105 %3:vgpr(s32) = G_FADD %1, %2 106 S_ENDPGM 0, implicit %3 107 108... 109 110--- 111 112name: fadd_s32_vvv_fneg_fabs_lhs 113legalized: true 114regBankSelected: true 115 116body: | 117 bb.0: 118 liveins: $vgpr0, $vgpr1 119 ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs 120 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 121 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 122 ; GFX6: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 123 ; GFX6: S_ENDPGM 0, implicit %4 124 %0:vgpr(s32) = COPY $vgpr0 125 %1:vgpr(s32) = COPY $vgpr1 126 %2:vgpr(s32) = G_FABS %0 127 %3:vgpr(s32) = G_FNEG %2 128 %4:vgpr(s32) = G_FADD %3, %1 129 S_ENDPGM 0, implicit %4 130 131... 132 133--- 134 135name: fadd_s32_vvv_fneg_fabs_rhs 136legalized: true 137regBankSelected: true 138 139body: | 140 bb.0: 141 liveins: $vgpr0, $vgpr1 142 ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs 143 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 144 ; GFX6: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec 145 ; GFX6: S_ENDPGM 0, implicit %4 146 %0:vgpr(s32) = COPY $vgpr0 147 %1:vgpr(s32) = COPY $vgpr1 148 %2:vgpr(s32) = G_FABS %1 149 %3:vgpr(s32) = G_FNEG %2 150 %4:vgpr(s32) = G_FADD %1, %3 151 S_ENDPGM 0, implicit %4 152 153... 154 155# Need to look through reg bank copy to find source modifiers 156--- 157 158name: fadd_s32_fneg_copy_sgpr 159legalized: true 160regBankSelected: true 161 162body: | 163 bb.0: 164 liveins: $vgpr0, $sgpr0 165 ; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr 166 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 167 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 168 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] 169 ; GFX6: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec 170 ; GFX6: S_ENDPGM 0, implicit %4 171 %0:vgpr(s32) = COPY $vgpr0 172 %1:sgpr(s32) = COPY $sgpr0 173 %2:sgpr(s32) = G_FNEG %1 174 %3:vgpr(s32) = COPY %2 175 %4:vgpr(s32) = G_FADD %0, %3 176 S_ENDPGM 0, implicit %4 177 178... 179 180# Need to look through copy in between fneg and fabs 181 182--- 183 184name: fadd_s32_copy_fneg_copy_fabs 185legalized: true 186regBankSelected: true 187 188body: | 189 bb.0: 190 liveins: $vgpr0, $sgpr0 191 ; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs 192 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 193 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 194 ; GFX6: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec 195 ; GFX6: S_ENDPGM 0, implicit %6 196 %0:vgpr(s32) = COPY $vgpr0 197 %1:sgpr(s32) = COPY $sgpr0 198 %2:sgpr(s32) = G_FABS %1 199 %3:sgpr(s32) = COPY %2 200 %4:sgpr(s32) = G_FNEG %3 201 %5:sgpr(s32) = COPY %4 202 %6:vgpr(s32) = G_FADD %0, %5 203 S_ENDPGM 0, implicit %6 204 205... 206 207# The source modifier lookup searches through SGPR->VGPR copies. Make 208# sure we don't violate the constant bus restriction when we look at 209# the source. 210 211--- 212 213name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr 214legalized: true 215regBankSelected: true 216 217body: | 218 bb.0: 219 liveins: $sgpr0, $sgpr1 220 ; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr 221 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 222 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 223 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] 224 ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] 225 ; GFX6: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec 226 ; GFX6: S_ENDPGM 0, implicit %6 227 %0:sgpr(s32) = COPY $sgpr0 228 %1:sgpr(s32) = COPY $sgpr1 229 %2:sgpr(s32) = G_FABS %0 230 %3:sgpr(s32) = G_FABS %1 231 %4:vgpr(s32) = COPY %2 232 %5:vgpr(s32) = COPY %3 233 %6:vgpr(s32) = G_FADD %4, %5 234 S_ENDPGM 0, implicit %6 235 236... 237 238--- 239 240name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr 241legalized: true 242regBankSelected: true 243 244body: | 245 bb.0: 246 liveins: $sgpr0, $sgpr1 247 ; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr 248 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 249 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 250 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] 251 ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] 252 ; GFX6: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec 253 ; GFX6: S_ENDPGM 0, implicit %6 254 %0:sgpr(s32) = COPY $sgpr0 255 %1:sgpr(s32) = COPY $sgpr1 256 %2:sgpr(s32) = G_FNEG %0 257 %3:sgpr(s32) = G_FNEG %1 258 %4:vgpr(s32) = COPY %2 259 %5:vgpr(s32) = COPY %3 260 %6:vgpr(s32) = G_FADD %4, %5 261 S_ENDPGM 0, implicit %6 262 263... 264 265--- 266 267name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr 268legalized: true 269regBankSelected: true 270 271body: | 272 bb.0: 273 liveins: $sgpr0, $sgpr1 274 ; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr 275 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 276 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 277 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] 278 ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] 279 ; GFX6: %8:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec 280 ; GFX6: S_ENDPGM 0, implicit %8 281 %0:sgpr(s32) = COPY $sgpr0 282 %1:sgpr(s32) = COPY $sgpr1 283 %2:sgpr(s32) = G_FABS %0 284 %3:sgpr(s32) = G_FABS %1 285 %4:sgpr(s32) = G_FNEG %2 286 %5:sgpr(s32) = G_FNEG %3 287 %6:vgpr(s32) = COPY %4 288 %7:vgpr(s32) = COPY %5 289 %8:vgpr(s32) = G_FADD %6, %7 290 S_ENDPGM 0, implicit %8 291 292... 293