Home
last modified time | relevance | path

Searched refs:zext (Results 1 – 25 of 4291) sorted by relevance

12345678910>>...172

/external/llvm/test/Analysis/BasicAA/
Dq.bad.ll9 %sext.zext.1 = zext i16 %sext.1 to i64
11 %sext.zext.2 = zext i32 %sext.2 to i64
12 %a = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.1
13 %b = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.2
19 ; %a and %b only PartialAlias as, although they're both zext(sext(%num)) they'll extend the sign by…
20 ; number of bits before zext-ing the remainder.
23 %sext.zext.1 = zext i16 %sext.1 to i64
25 %sext.zext.2 = zext i32 %sext.2 to i64
26 %a = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.1
27 %b = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.2
[all …]
/external/llvm-project/llvm/test/Analysis/BasicAA/
Dq.bad.ll9 %sext.zext.1 = zext i16 %sext.1 to i64
11 %sext.zext.2 = zext i32 %sext.2 to i64
12 %a = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.1
13 %b = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.2
19 ; %a and %b only PartialAlias as, although they're both zext(sext(%num)) they'll extend the sign by…
20 ; number of bits before zext-ing the remainder.
23 %sext.zext.1 = zext i16 %sext.1 to i64
25 %sext.zext.2 = zext i32 %sext.2 to i64
26 %a = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.1
27 %b = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.2
[all …]
/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Dzext-divrem.ll7 %zext = zext i32 %div to i64
8 ; CHECK: %zext
9 ; CHECK-NEXT: --> ((zext i32 %a to i64) /u (zext i32 %b to i64))
10 ret i64 %zext
16 %zext = zext i32 %rem to i64
17 ; CHECK: %zext
18 ; CHECK-NEXT: --> ((zext i32 %a to i64) + (-1 * (zext i32 %b to i64) * ((zext i32 %a to i64) /u (z…
19 ret i64 %zext
27 %zext = zext i32 %sub to i64
28 ; CHECK: %zext
[all …]
Dumin-umax-folds.ll8 ; CHECK-NEXT: %len.zext = zext i32 %len to i64
9 ; CHECK-NEXT: --> (zext i32 %len to i64) U: [0,4294967296) S: [0,4294967296)
13 ; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,4294967296) S: [0,4294967296) Exits: (zext i32 %len to i6…
15 ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4294967297) S: [1,4294967297) Exits: (1 + (zext i32 %len …
19 ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i32 %len to i64)
21 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i32 %len to i64)
26 %len.zext = zext i32 %len to i64
32 %cmp1 = icmp ult i64 %iv, %len.zext
43 ; CHECK-NEXT: %len.zext = zext i32 %len to i64
44 ; CHECK-NEXT: --> (zext i32 %len to i64) U: [0,4294967296) S: [0,4294967296)
[all …]
Dno-wrap-add-exprs.ll63 ; CHECK-NEXT: --> (-1 + (zext i8 %len to i16))<nsw> U: [-1,126) S: [-1,126)
65 ; CHECK-NEXT: --> (-2 + (zext i8 %len to i16))<nsw> U: [-2,125) S: [-2,125)
106 ; CHECK-NEXT: %t0.zext = zext i8 %t0 to i16
107 ; CHECK-NEXT: --> (1 + (zext i8 %len to i16))<nuw><nsw> U: [1,128) S: [1,128)
108 ; CHECK-NEXT: %t1.zext = zext i8 %t1 to i16
109 ; CHECK-NEXT: --> (2 + (zext i8 %len to i16))<nuw><nsw> U: [2,129) S: [2,129)
114 ; CHECK-NEXT: %q0.zext = zext i8 %q0 to i16
115 ; CHECK-NEXT: --> (zext i8 (1 + %len_norange) to i16) U: [0,256) S: [0,256)
116 ; CHECK-NEXT: %q1.zext = zext i8 %q1 to i16
117 ; CHECK-NEXT: --> (zext i8 (2 + %len_norange) to i16) U: [0,256) S: [0,256)
[all …]
/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dcmp_ext.ll7 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X]] to i64
12 %zext = zext i32 %x to i64
13 %cmp = icmp uge i64 %zext, %sext
22 %zext = zext i32 %x to i64
23 %cmp = icmp ugt i64 %zext, %sext
30 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X]] to i64
35 %zext = zext i32 %x to i64
36 %cmp = icmp ult i64 %zext, %sext
45 %zext = zext i32 %x to i64
46 %cmp = icmp ule i64 %zext, %sext
[all …]
/external/llvm/test/Transforms/InstCombine/
Doverflow-mul.ll3 ; return mul(zext x, zext y) > MAX
7 %l = zext i32 %x to i64
8 %r = zext i32 %y to i64
9 ; CHECK-NOT: zext i32
14 %retval = zext i1 %overflow to i32
18 ; return mul(zext x, zext y) >= MAX+1
22 %l = zext i32 %x to i64
23 %r = zext i32 %y to i64
24 ; CHECK-NOT: zext i32
29 %retval = zext i1 %overflow to i32
[all …]
Dzext.ll6 ; CHECK-NEXT: [[C2:%.*]] = zext i16 %A to i64
9 %c1 = zext i16 %A to i32
16 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> %A to <2 x i64>
21 %zext = zext <2 x i1> %xor to <2 x i64>
22 ret <2 x i64> %zext
32 %zext = zext <2 x i32> %and to <2 x i64>
33 ret <2 x i64> %zext
45 %zext = zext <2 x i32> %xor to <2 x i64>
46 ret <2 x i64> %zext
53 ; CHECK-NEXT: [[ZEXT1:%.*]] = zext i1 %a to i32
[all …]
Dudivrem-change-width.ll7 %conv = zext i8 %a to i32
8 %conv2 = zext i8 %b to i32
17 %conv = zext i8 %a to i32
18 %conv2 = zext i8 %b to i32
27 %conv = zext i8 %a to i32
28 %conv2 = zext i8 %b to i32
33 ; CHECK: zext
37 %conv = zext i8 %a to i32
38 %conv2 = zext i8 %b to i32
43 ; CHECK: zext
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Doverflow-mul.ll14 ; return mul(zext x, zext y) > MAX
18 %l = zext i32 %x to i64
19 %r = zext i32 %y to i64
20 ; CHECK-NOT: zext i32
25 %retval = zext i1 %overflow to i32
29 ; return mul(zext x, zext y) >= MAX+1
33 %l = zext i32 %x to i64
34 %r = zext i32 %y to i64
35 ; CHECK-NOT: zext i32
40 %retval = zext i1 %overflow to i32
[all …]
Dudivrem-change-width.ll11 %za = zext i8 %a to i32
12 %zb = zext i8 %b to i32
23 %za = zext <2 x i8> %a to <2 x i32>
24 %zb = zext <2 x i8> %b to <2 x i32>
35 %za = zext i8 %a to i32
36 %zb = zext i8 %b to i32
47 %za = zext <2 x i8> %a to <2 x i32>
48 %zb = zext <2 x i8> %b to <2 x i32>
57 ; CHECK-NEXT: [[UDIV:%.*]] = zext i8 [[DIV]] to i32
60 %za = zext i8 %a to i32
[all …]
Dzext.ll6 ; CHECK-NEXT: [[C2:%.*]] = zext i16 [[A:%.*]] to i64
9 %c1 = zext i16 %A to i32
17 ; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i1> [[XOR]] to <2 x i64>
21 %zext = zext <2 x i1> %xor to <2 x i64>
22 ret <2 x i64> %zext
32 %zext = zext <2 x i32> %and to <2 x i64>
33 ret <2 x i64> %zext
45 %zext = zext <2 x i32> %xor to <2 x i64>
46 ret <2 x i64> %zext
52 ; CHECK-NEXT: [[ZEXT2:%.*]] = zext i1 [[TMP1]] to i64
[all …]
Dor-concat.ll6 ; or(zext(OP(x)), shl(zext(OP(y)),bw/2))
8 ; OP(or(zext(x), shl(zext(y),bw/2)))
24 %6 = zext i32 %4 to i64
25 %7 = zext i32 %5 to i64
41 %6 = zext <2 x i32> %4 to <2 x i64>
42 %7 = zext <2 x i32> %5 to <2 x i64>
59 %6 = zext i32 %4 to i64
60 %7 = zext i32 %5 to i64
77 %6 = zext <2 x i32> %4 to <2 x i64>
78 %7 = zext <2 x i32> %5 to <2 x i64>
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dglobal-saddr-store.ll15 %zext.offset = zext i32 %voffset to i64
16 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
30 %zext.offset = zext i32 %voffset to i64
31 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
46 %zext.offset = zext i32 %voffset to i64
47 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
72 %zext.offset = zext i32 %voffset to i64
73 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
91 %zext.offset = zext i32 %voffset to i64
92 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
[all …]
Dglobal-saddr-load.ll20 %zext = zext i8 %load to i32
21 %to.vgpr = bitcast i32 %zext to float
42 %zext = zext i8 %load to i32
43 %to.vgpr = bitcast i32 %zext to float
57 %zext = zext i8 %load to i32
58 %to.vgpr = bitcast i32 %zext to float
72 %zext = zext i8 %load to i32
73 %to.vgpr = bitcast i32 %zext to float
95 %zext = zext i8 %load to i32
96 %to.vgpr = bitcast i32 %zext to float
[all …]
/external/llvm/test/Transforms/LoadCombine/
Dload-combine.ll10 %3 = zext i8 %2 to i64
14 %7 = zext i8 %6 to i64
19 %12 = zext i8 %11 to i64
24 %17 = zext i8 %16 to i64
29 %22 = zext i8 %21 to i64
34 %27 = zext i8 %26 to i64
39 %32 = zext i8 %31 to i64
44 %37 = zext i8 %36 to i64
57 %4 = zext i16 %3 to i32
59 %6 = zext i16 %1 to i32
[all …]
/external/llvm/test/Transforms/SLPVectorizer/AArch64/
Dgather-reduce.ll25 ; GENERIC: zext <8 x i16> [[L]] to <8 x i32>
51 %conv = zext i16 %0 to i32
54 %conv2 = zext i16 %1 to i32
58 %conv3 = zext i16 %2 to i32
62 %conv5 = zext i16 %3 to i32
65 %conv7 = zext i16 %4 to i32
69 %conv11 = zext i16 %5 to i32
73 %conv14 = zext i16 %6 to i32
76 %conv16 = zext i16 %7 to i32
80 %conv20 = zext i16 %8 to i32
[all …]
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll35 %res0 = zext <4 x i1> %res0_i1 to <4 x i32>
39 %res1 = zext <4 x i1> %res1_i1 to <4 x i32>
43 %res2 = zext <4 x i1> %res2_i1 to <4 x i32>
47 %res3 = zext <4 x i1> %res3_i1 to <4 x i32>
68 %res0 = zext <8 x i1> %res0_i1 to <8 x i16>
72 %res1 = zext <8 x i1> %res1_i1 to <8 x i16>
76 %res2 = zext <8 x i1> %res2_i1 to <8 x i16>
80 %res3 = zext <8 x i1> %res3_i1 to <8 x i16>
84 %res4 = zext <8 x i1> %res4_i1 to <8 x i16>
88 %res5 = zext <8 x i1> %res5_i1 to <8 x i16>
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-conv-11.ll77 %ext0 = zext i8 %trunc0 to i32
78 %ext1 = zext i8 %trunc1 to i32
79 %ext2 = zext i8 %trunc2 to i32
80 %ext3 = zext i8 %trunc3 to i32
81 %ext4 = zext i8 %trunc4 to i32
82 %ext5 = zext i8 %trunc5 to i32
83 %ext6 = zext i8 %trunc6 to i32
84 %ext7 = zext i8 %trunc7 to i32
85 %ext8 = zext i8 %trunc8 to i32
86 %ext9 = zext i8 %trunc9 to i32
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dint-conv-11.ll77 %ext0 = zext i8 %trunc0 to i32
78 %ext1 = zext i8 %trunc1 to i32
79 %ext2 = zext i8 %trunc2 to i32
80 %ext3 = zext i8 %trunc3 to i32
81 %ext4 = zext i8 %trunc4 to i32
82 %ext5 = zext i8 %trunc5 to i32
83 %ext6 = zext i8 %trunc6 to i32
84 %ext7 = zext i8 %trunc7 to i32
85 %ext8 = zext i8 %trunc8 to i32
86 %ext9 = zext i8 %trunc9 to i32
[all …]
/external/llvm/test/Analysis/ScalarEvolution/
Dno-wrap-add-exprs.ll66 ; CHECK-NEXT: --> (-1 + (zext i8 %len to i16))<nsw> U: [-1,126) S: [-1,126)
68 ; CHECK-NEXT: --> (-2 + (zext i8 %len to i16))<nsw> U: [-2,125) S: [-2,125)
104 %t0.zext = zext i8 %t0 to i16
105 %t1.zext = zext i8 %t1 to i16
106 ; CHECK: %t0.zext = zext i8 %t0 to i16
107 ; CHECK-NEXT: --> (1 + (zext i8 %len to i16))<nuw><nsw> U: [1,128) S: [1,128)
108 ; CHECK: %t1.zext = zext i8 %t1 to i16
109 ; CHECK-NEXT: --> (2 + (zext i8 %len to i16))<nuw><nsw> U: [2,129) S: [2,129)
113 %q0.zext = zext i8 %q0 to i16
114 %q1.zext = zext i8 %q1 to i16
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-masked-gather-32b-unsigned-unscaled.ll14 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
15 %ptrs = getelementptr i8, i8* %base, <vscale x 2 x i64> %offsets.zext
17 %vals.zext = zext <vscale x 2 x i8> %vals to <vscale x 2 x i64>
18 ret <vscale x 2 x i64> %vals.zext
26 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
27 %byte_ptrs = getelementptr i8, i8* %base, <vscale x 2 x i64> %offsets.zext
30 %vals.zext = zext <vscale x 2 x i16> %vals to <vscale x 2 x i64>
31 ret <vscale x 2 x i64> %vals.zext
39 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
40 %byte_ptrs = getelementptr i8, i8* %base, <vscale x 2 x i64> %offsets.zext
[all …]
/external/llvm/test/CodeGen/X86/
D2008-12-02-IllegalResultType.ll12 %2 = zext i8 %1 to i64 ; <i64> [#uses=1]
14 %4 = zext i1 %3 to i64 ; <i64> [#uses=1]
17 %7 = zext i1 %6 to i8 ; <i8> [#uses=1]
19 %9 = zext i8 %8 to i64 ; <i64> [#uses=1]
21 %11 = zext i1 %10 to i8 ; <i8> [#uses=1]
23 %13 = zext i8 %12 to i64 ; <i64> [#uses=1]
25 %15 = zext i1 %14 to i8 ; <i8> [#uses=1]
27 %17 = zext i8 %16 to i64 ; <i64> [#uses=1]
29 %19 = zext i1 %18 to i8 ; <i8> [#uses=1]
31 %21 = zext i8 %20 to i64 ; <i64> [#uses=1]
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvmlldav.ll26 %5 = zext i32 %4 to i64
29 %8 = zext i32 %7 to i64
45 %5 = zext i32 %4 to i64
48 %8 = zext i32 %7 to i64
64 %5 = zext i32 %4 to i64
67 %8 = zext i32 %7 to i64
83 %5 = zext i32 %4 to i64
86 %8 = zext i32 %7 to i64
102 %5 = zext i32 %4 to i64
105 %8 = zext i32 %7 to i64
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvshll.ll34 %zext = zext <8 x i8> %tmp1 to <8 x i16>
35 %shift = shl <8 x i16> %zext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
43 %zext = zext <4 x i16> %tmp1 to <4 x i32>
44 %shift = shl <4 x i32> %zext, <i32 15, i32 15, i32 15, i32 15>
52 %zext = zext <2 x i32> %tmp1 to <2 x i64>
53 %shift = shl <2 x i64> %zext, <i64 31, i64 31>
72 %zext = zext <4 x i16> %tmp1 to <4 x i32>
73 %shift = shl <4 x i32> %zext, <i32 16, i32 16, i32 16, i32 16>
81 %zext = zext <2 x i32> %tmp1 to <2 x i64>
82 %shift = shl <2 x i64> %zext, <i64 32, i64 32>
[all …]

12345678910>>...172