| /external/llvm-project/llvm/lib/Transforms/Utils/ |
| D | AddDiscriminators.cpp | 184 LocationDiscriminatorMap LDM; in addDiscriminators() local
211 unsigned Discriminator = R.second ? ++LDM[L] : LDM[L]; in addDiscriminators()
248 unsigned Discriminator = ++LDM[L]; in addDiscriminators()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | AddDiscriminators.cpp | 184 LocationDiscriminatorMap LDM; in addDiscriminators() local
211 unsigned Discriminator = R.second ? ++LDM[L] : LDM[L]; in addDiscriminators()
248 unsigned Discriminator = ++LDM[L]; in addDiscriminators()
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| /external/llvm/lib/Transforms/Utils/ |
| D | AddDiscriminators.cpp | 180 LocationDiscriminatorMap LDM; in addDiscriminators() local
205 NewScope = Builder.createLexicalBlockFile(Scope, File, ++LDM[L]); in addDiscriminators()
237 auto *NewScope = Builder.createLexicalBlockFile(Scope, File, ++LDM[L]); in addDiscriminators()
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | t2-shrink-ldrpost.ll | 7 ; NOTE: When optimising for minimum size, an LDM is expected to be generated
42 ; NOTE: When not optimising for minimum size, an LDM is expected not to be generated
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| D | 2010-10-25-ifcvt-ldm.ll | 3 ; LDM instruction, was causing an assertion failure because the microop count
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| D | cortex-a57-misched-ldm.ll | 5 ; We need second, post-ra scheduling to have LDM instruction combined from single-loads
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| D | cortex-a57-misched-ldm-wrback.ll | 10 ; We need second, post-ra scheduling to have LDM instruction combined from single-loads
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| D | 2013-04-16-AAPCS-C4-vs-VFP.ll | 24 ;registers from memory using an LDM instruction. The argument has now been
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2010-10-25-ifcvt-ldm.ll | 3 ; LDM instruction, was causing an assertion failure because the microop count
|
| D | 2013-04-16-AAPCS-C4-vs-VFP.ll | 24 ;registers from memory using an LDM instruction. The argument has now been
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleM4.td | 55 def : M4UnitL2I<(instregex "(t|t2)LDM")>;
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| D | ARMScheduleR52.td | 480 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
481 "(t|sys)LDM(IA|DA|DB|IB)$")>;
483 (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
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| D | ARMScheduleSwift.td | 482 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
483 "(t|sys)LDM(IA|DA|DB|IB)$")>;
486 "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
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| D | ARMScheduleM7.td | 236 (instregex "(t|t2)LDM(DB|IA)$")>;
240 (instregex "(t|t2)LDM(DB|IA)_UPD$", "tPOP")>;
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| D | ARMScheduleA9.td | 2049 // Define a predicate to select the LDM based on number of memory addresses.
2058 // LDM/VLDM/VLDn address generation latency & resources.
2069 // For unknown LDM/VLDM/VSTM, assume 2 32-bit registers.
2072 // Define LDM Resources.
2092 // LDM: Load multiple into 32-bit integer registers.
2247 // tuple, unlike LDM. So the number of write operands is not variadic.
2253 // Resources for other (non-LDM/VLDM) Variants.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleM4.td | 55 def : M4UnitL2I<(instregex "(t|t2)LDM")>;
|
| D | ARMScheduleR52.td | 480 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
481 "(t|sys)LDM(IA|DA|DB|IB)$")>;
483 (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
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| D | ARMScheduleSwift.td | 482 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
483 "(t|sys)LDM(IA|DA|DB|IB)$")>;
486 "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
|
| D | ARMScheduleA9.td | 2049 // Define a predicate to select the LDM based on number of memory addresses.
2058 // LDM/VLDM/VLDn address generation latency & resources.
2069 // For unknown LDM/VLDM/VSTM, assume 2 32-bit registers.
2072 // Define LDM Resources.
2092 // LDM: Load multiple into 32-bit integer registers.
2247 // tuple, unlike LDM. So the number of write operands is not variadic.
2253 // Resources for other (non-LDM/VLDM) Variants.
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 147 # LDM
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| D | invalid-armv7.txt | 105 # A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 147 # LDM
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 466 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
467 "(t|sys)LDM(IA|DA|DB|IB)$")>;
470 "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
|
| D | ARMScheduleA9.td | 2026 // Define a predicate to select the LDM based on number of memory addresses.
2035 // LDM/VLDM/VLDn address generation latency & resources.
2046 // For unknown LDM/VLDM/VSTM, assume 2 32-bit registers.
2049 // Define LDM Resources.
2069 // LDM: Load multiple into 32-bit integer registers.
2224 // tuple, unlike LDM. So the number of write operands is not variadic.
2230 // Resources for other (non-LDM/VLDM) Variants.
|
| /external/llvm/test/MC/ARM/ |
| D | thumb-diagnostics.s | 58 @ Invalid writeback and register lists for LDM
|