1; REQUIRES: asserts
2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
3;
4
5@a = global i32 0, align 4
6@b = global i32 0, align 4
7@c = global i32 0, align 4
8
9; CHECK:       ********** MI Scheduling **********
10; We need second, post-ra scheduling to have LDM instruction combined from single-loads
11; CHECK:       ********** MI Scheduling **********
12; CHECK:       LDMIA_UPD
13; CHECK:       rdefs left
14; CHECK-NEXT:  Latency            : 4
15; CHECK:       Successors:
16; CHECK:       Data
17; CHECK-SAME:  Latency=1
18; CHECK-NEXT:  Data
19; CHECK-SAME:  Latency=3
20; CHECK-NEXT:  Data
21; CHECK-SAME:  Latency=0
22; CHECK-NEXT:  Data
23; CHECK-SAME:  Latency=0
24define i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
25  %1 = load i32, i32* @a, align 4
26  %2 = load i32, i32* @b, align 4
27  %3 = load i32, i32* @c, align 4
28
29  %ptr_after = getelementptr i32, i32* @a, i32 3
30
31  %ptr_val = ptrtoint i32* %ptr_after to i32
32  %mul1 = mul i32 %ptr_val, %1
33  %mul2 = mul i32 %mul1, %2
34  %mul3 = mul i32 %mul2, %3
35  ret i32 %mul3
36}
37
38