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/external/llvm/test/MC/ARM/
Dneont2-abs-encoding.s5 @ CHECK: vabs.s8 d16, d16 @ encoding: [0xf1,0xff,0x20,0x03]
6 vabs.s8 d16, d16
7 @ CHECK: vabs.s16 d16, d16 @ encoding: [0xf5,0xff,0x20,0x03]
8 vabs.s16 d16, d16
9 @ CHECK: vabs.s32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x03]
10 vabs.s32 d16, d16
11 @ CHECK: vabs.f32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x07]
12 vabs.f32 d16, d16
13 @ CHECK: vabs.s8 q8, q8 @ encoding: [0xf1,0xff,0x60,0x03]
14 vabs.s8 q8, q8
[all …]
Dneon-abs-encoding.s3 @ CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3]
4 vabs.s8 d16, d16
5 @ CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xf3]
6 vabs.s16 d16, d16
7 @ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xf3]
8 vabs.s32 d16, d16
9 @ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xf3]
10 vabs.f32 d16, d16
11 @ CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xf3]
12 vabs.s8 q8, q8
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dneon-abs-encoding.s3 @ CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3]
4 vabs.s8 d16, d16
5 @ CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xf3]
6 vabs.s16 d16, d16
7 @ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xf3]
8 vabs.s32 d16, d16
9 @ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xf3]
10 vabs.f32 d16, d16
11 @ CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xf3]
12 vabs.s8 q8, q8
[all …]
Dneont2-abs-encoding.s5 @ CHECK: vabs.s8 d16, d16 @ encoding: [0xf1,0xff,0x20,0x03]
6 vabs.s8 d16, d16
7 @ CHECK: vabs.s16 d16, d16 @ encoding: [0xf5,0xff,0x20,0x03]
8 vabs.s16 d16, d16
9 @ CHECK: vabs.s32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x03]
10 vabs.s32 d16, d16
11 @ CHECK: vabs.f32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x07]
12 vabs.f32 d16, d16
13 @ CHECK: vabs.s8 q8, q8 @ encoding: [0xf1,0xff,0x60,0x03]
14 vabs.s8 q8, q8
[all …]
/external/capstone/suite/MC/ARM/
Dneon-abs-encoding.s.cs2 0x20,0x03,0xf1,0xf3 = vabs.s8 d16, d16
3 0x20,0x03,0xf5,0xf3 = vabs.s16 d16, d16
4 0x20,0x03,0xf9,0xf3 = vabs.s32 d16, d16
5 0x20,0x07,0xf9,0xf3 = vabs.f32 d16, d16
6 0x60,0x03,0xf1,0xf3 = vabs.s8 q8, q8
7 0x60,0x03,0xf5,0xf3 = vabs.s16 q8, q8
8 0x60,0x03,0xf9,0xf3 = vabs.s32 q8, q8
9 0x60,0x07,0xf9,0xf3 = vabs.f32 q8, q8
Dneont2-abs-encoding.s.cs2 0xf1,0xff,0x20,0x03 = vabs.s8 d16, d16
3 0xf5,0xff,0x20,0x03 = vabs.s16 d16, d16
4 0xf9,0xff,0x20,0x03 = vabs.s32 d16, d16
5 0xf9,0xff,0x20,0x07 = vabs.f32 d16, d16
6 0xf1,0xff,0x60,0x03 = vabs.s8 q8, q8
7 0xf5,0xff,0x60,0x03 = vabs.s16 q8, q8
8 0xf9,0xff,0x60,0x03 = vabs.s32 q8, q8
9 0xf9,0xff,0x60,0x07 = vabs.f32 q8, q8
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvabs.ll5 ;CHECK: vabs.s8
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
23 …%tmp1 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> <i8 -128, i8 -127, i8 -1, i8 0, i8 1, i8 1…
29 ;CHECK: vabs.s16
31 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
43 …%tmp1 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> <i16 -32768, i16 -32767, i16 255, i16 3…
49 ;CHECK: vabs.s32
51 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
61 %tmp1 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> <i32 -2147483647, i32 2147483648>)
67 ;CHECK: vabs.f32
[all …]
Dfp16-vector-argument.ll14 ; SOFT-NEXT: vabs.f16 d16, d16
20 ; HARD-NEXT: vabs.f16 d0, d0
27 ; SOFTEB-NEXT: vabs.f16 d16, d16
35 ; HARDEB-NEXT: vabs.f16 d16, d16
49 ; SOFT-NEXT: vabs.f16 q8, q8
56 ; HARD-NEXT: vabs.f16 q0, q0
64 ; SOFTEB-NEXT: vabs.f16 q8, q8
73 ; HARDEB-NEXT: vabs.f16 q8, q8
88 ; SOFT-NEXT: vabs.f16 d16, d16
93 ; SOFT-NEXT: vabs.f16 q8, q8
[all …]
Dfabss.ll17 ; VFP2: vabs.f32 s
20 ; NFP1: vabs.f32 d
22 ; NFP0: vabs.f32 s
26 ; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]]
29 ; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
Dfabs-neon.ll4 ; CHECK: vabs.f32 q0, q0
12 ; CHECK: vabs.f32 d0, d0
27 ; vabs.f32 d16, d16
40 ; CHECK-NOT: vabs
51 ; CHECK-NOT: vabs
Dneon_vabs.ll9 ; CHECK-NEXT: vabs.s32 q8, q8
24 ; CHECK-NEXT: vabs.s32 q8, q8
39 ; CHECK-NEXT: vabs.s16 q8, q8
54 ; CHECK-NEXT: vabs.s8 q8, q8
69 ; CHECK-NEXT: vabs.s32 q8, q8
83 ; CHECK-NEXT: vabs.s32 d16, d16
96 ; CHECK-NEXT: vabs.s32 d16, d16
109 ; CHECK-NEXT: vabs.s16 d16, d16
122 ; CHECK-NEXT: vabs.s8 d16, d16
135 ; CHECK-NEXT: vabs.s32 d16, d16
Dfp16-intrinsic-vector-1op.ll11 ; CHECK-HARD: vabs.f16 q0, q0
15 ; CHECK-HARD-BE-NEXT: vabs.f16 [[Q8]], [[Q8]]
21 ; CHECK-SOFTFP: vabs.f16 q{{.*}}, q{{.*}}
29 ; CHECK-SOFTFP-BE: vabs.f16 [[Q8]], [[Q8]]
D2012-08-27-CopyPhysRegCrash.ll43 %28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind
57 %42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind
58 %43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind
80 %65 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %60) nounwind
87 %72 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> undef) nounwind
88 %73 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %71) nounwind
96 %81 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %80) nounwind
129 declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
/external/llvm/test/CodeGen/ARM/
Dvabs.ll5 ;CHECK: vabs.s8
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
13 ;CHECK: vabs.s16
15 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
21 ;CHECK: vabs.s32
23 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
29 ;CHECK: vabs.f32
37 ;CHECK: vabs.s8
39 %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
45 ;CHECK: vabs.s16
[all …]
Dfabss.ll17 ; VFP2: vabs.f32 s
20 ; NFP1: vabs.f32 d
22 ; NFP0: vabs.f32 s
26 ; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]]
29 ; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
Dneon_vabs.ll5 ; CHECK: vabs.s32 q
14 ; CHECK: vabs.s32 q
23 ; CHECK: vabs.s16 q
32 ; CHECK: vabs.s8 q
41 ; CHECK: vabs.s32 q
50 ; CHECK: vabs.s32 d
59 ; CHECK: vabs.s32 d
68 ; CHECK: vabs.s16 d
77 ; CHECK: vabs.s8 d
86 ; CHECK: vabs.s32 d
Dfabs-neon.ll4 ; CHECK: vabs.f32 q0, q0
12 ; CHECK: vabs.f32 d0, d0
27 ; vabs.f32 d16, d16
40 ; CHECK-NOT: vabs
51 ; CHECK-NOT: vabs
D2012-08-27-CopyPhysRegCrash.ll43 %28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind
57 %42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind
58 %43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind
80 %65 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %60) nounwind
87 %72 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> undef) nounwind
88 %73 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %71) nounwind
96 %81 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %80) nounwind
129 declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
/external/XNNPACK/scripts/
Dgenerate-f32-vunary.sh9 tools/xngen src/f32-vunary/scalar.c.in -D OP=ABS -D BATCH_TILE=1 -o src/f32-vunary/gen/vabs-scalar-…
10 tools/xngen src/f32-vunary/scalar.c.in -D OP=ABS -D BATCH_TILE=2 -o src/f32-vunary/gen/vabs-scalar-…
11 tools/xngen src/f32-vunary/scalar.c.in -D OP=ABS -D BATCH_TILE=4 -o src/f32-vunary/gen/vabs-scalar-…
20 tools/xngen src/f32-vunary/wasmsimd.c.in -D OP=ABS -D BATCH_TILE=4 -o src/f32-vunary/gen/vabs-wasms…
21 tools/xngen src/f32-vunary/wasmsimd.c.in -D OP=ABS -D BATCH_TILE=8 -o src/f32-vunary/gen/vabs-wasms…
28 tools/xngen src/f32-vunary/neon.c.in -D OP=ABS -D BATCH_TILE=4 -o src/f32-vunary/gen/vabs-neon-x4.c
29 tools/xngen src/f32-vunary/neon.c.in -D OP=ABS -D BATCH_TILE=8 -o src/f32-vunary/gen/vabs-neon-x8.c
36 tools/xngen src/f32-vunary/sse.c.in -D OP=ABS -D BATCH_TILE=4 -o src/f32-vunary/gen/vabs-sse-x4.c
37 tools/xngen src/f32-vunary/sse.c.in -D OP=ABS -D BATCH_TILE=8 -o src/f32-vunary/gen/vabs-sse-x8.c
44 tools/xngen src/f32-vunary/avx.c.in -D OP=ABS -D BATCH_TILE=8 -o src/f32-vunary/gen/vabs-avx-x8.c
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-fp-negabs.ll93 ; CHECK-MVE-NEXT: vabs.f16 s8, s1
94 ; CHECK-MVE-NEXT: vabs.f16 s4, s4
96 ; CHECK-MVE-NEXT: vabs.f16 s4, s0
100 ; CHECK-MVE-NEXT: vabs.f16 s0, s0
105 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
107 ; CHECK-MVE-NEXT: vabs.f16 s8, s2
112 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
114 ; CHECK-MVE-NEXT: vabs.f16 s8, s3
125 ; CHECK-MVEFP-NEXT: vabs.f16 q0, q0
135 ; CHECK-MVE-NEXT: vabs.f32 s7, s3
[all …]
Dmve-abs.ll7 ; CHECK-NEXT: vabs.s8 q0, q0
19 ; CHECK-NEXT: vabs.s16 q0, q0
31 ; CHECK-NEXT: vabs.s32 q0, q0
/external/llvm-project/llvm/test/CodeGen/Thumb/
Diabs-vector.ll8 ; CHECK-NEXT: vabs.s32 q8, q8
11 ; CHECK-NEXT: vabs.s32 q8, q8
/external/llvm-project/llvm/test/MC/Hexagon/
Dv65_all.s151 V0.b=vabs(V0.b)
152 # CHECK: 1e01c080 { v0.b = vabs(v0.b) }
171 V0.b=vabs(V0.b):sat
172 # CHECK: 1e01c0a0 { v0.b = vabs(v0.b):sat }
Dv60-alu.s290 #CHECK: 1e00df70 { v16.w = vabs(v31.w):sat }
291 v16.w=vabs(v31.w):sat
293 #CHECK: 1e00d45f { v31.w = vabs(v20.w) }
294 v31.w=vabs(v20.w)
296 #CHECK: 1e00db2f { v15.h = vabs(v27.h):sat }
297 v15.h=vabs(v27.h):sat
299 #CHECK: 1e00d001 { v1.h = vabs(v16.h) }
300 v1.h=vabs(v16.h)
/external/llvm/test/MC/Hexagon/
Dv60-alu.s290 #CHECK: 1e00df70 { v16.w = vabs(v31.w):sat }
291 v16.w=vabs(v31.w):sat
293 #CHECK: 1e00d45f { v31.w = vabs(v20.w) }
294 v31.w=vabs(v20.w)
296 #CHECK: 1e00db2f { v15.h = vabs(v27.h):sat }
297 v15.h=vabs(v27.h):sat
299 #CHECK: 1e00d001 { v1.h = vabs(v16.h) }
300 v1.h=vabs(v16.h)

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