1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
4
5define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
6; CHECK-MVE-LABEL: fneg_float16_t:
7; CHECK-MVE:       @ %bb.0: @ %entry
8; CHECK-MVE-NEXT:    vmovx.f16 s4, s0
9; CHECK-MVE-NEXT:    vneg.f16 s8, s1
10; CHECK-MVE-NEXT:    vneg.f16 s4, s4
11; CHECK-MVE-NEXT:    vmov r0, s4
12; CHECK-MVE-NEXT:    vneg.f16 s4, s0
13; CHECK-MVE-NEXT:    vmov r1, s4
14; CHECK-MVE-NEXT:    vmovx.f16 s0, s3
15; CHECK-MVE-NEXT:    vmov.16 q1[0], r1
16; CHECK-MVE-NEXT:    vneg.f16 s0, s0
17; CHECK-MVE-NEXT:    vmov.16 q1[1], r0
18; CHECK-MVE-NEXT:    vmov r0, s8
19; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
20; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
21; CHECK-MVE-NEXT:    vneg.f16 s8, s8
22; CHECK-MVE-NEXT:    vmov r0, s8
23; CHECK-MVE-NEXT:    vneg.f16 s8, s2
24; CHECK-MVE-NEXT:    vmov.16 q1[3], r0
25; CHECK-MVE-NEXT:    vmov r0, s8
26; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
27; CHECK-MVE-NEXT:    vmov.16 q1[4], r0
28; CHECK-MVE-NEXT:    vneg.f16 s8, s8
29; CHECK-MVE-NEXT:    vmov r0, s8
30; CHECK-MVE-NEXT:    vneg.f16 s8, s3
31; CHECK-MVE-NEXT:    vmov.16 q1[5], r0
32; CHECK-MVE-NEXT:    vmov r0, s8
33; CHECK-MVE-NEXT:    vmov.16 q1[6], r0
34; CHECK-MVE-NEXT:    vmov r0, s0
35; CHECK-MVE-NEXT:    vmov.16 q1[7], r0
36; CHECK-MVE-NEXT:    vmov q0, q1
37; CHECK-MVE-NEXT:    bx lr
38;
39; CHECK-MVEFP-LABEL: fneg_float16_t:
40; CHECK-MVEFP:       @ %bb.0: @ %entry
41; CHECK-MVEFP-NEXT:    vneg.f16 q0, q0
42; CHECK-MVEFP-NEXT:    bx lr
43entry:
44  %0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src
45  ret <8 x half> %0
46}
47
48define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {
49; CHECK-MVE-LABEL: fneg_float32_t:
50; CHECK-MVE:       @ %bb.0: @ %entry
51; CHECK-MVE-NEXT:    vneg.f32 s7, s3
52; CHECK-MVE-NEXT:    vneg.f32 s6, s2
53; CHECK-MVE-NEXT:    vneg.f32 s5, s1
54; CHECK-MVE-NEXT:    vneg.f32 s4, s0
55; CHECK-MVE-NEXT:    vmov q0, q1
56; CHECK-MVE-NEXT:    bx lr
57;
58; CHECK-MVEFP-LABEL: fneg_float32_t:
59; CHECK-MVEFP:       @ %bb.0: @ %entry
60; CHECK-MVEFP-NEXT:    vneg.f32 q0, q0
61; CHECK-MVEFP-NEXT:    bx lr
62entry:
63  %0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src
64  ret <4 x float> %0
65}
66
67define arm_aapcs_vfpcc <2 x double> @fneg_float64_t(<2 x double> %src) {
68; CHECK-LABEL: fneg_float64_t:
69; CHECK:       @ %bb.0: @ %entry
70; CHECK-NEXT:    .pad #16
71; CHECK-NEXT:    sub sp, #16
72; CHECK-NEXT:    vstr d1, [sp]
73; CHECK-NEXT:    ldrb.w r0, [sp, #7]
74; CHECK-NEXT:    vstr d0, [sp, #8]
75; CHECK-NEXT:    ldrb.w r1, [sp, #15]
76; CHECK-NEXT:    eor r0, r0, #128
77; CHECK-NEXT:    strb.w r0, [sp, #7]
78; CHECK-NEXT:    vldr d1, [sp]
79; CHECK-NEXT:    eor r0, r1, #128
80; CHECK-NEXT:    strb.w r0, [sp, #15]
81; CHECK-NEXT:    vldr d0, [sp, #8]
82; CHECK-NEXT:    add sp, #16
83; CHECK-NEXT:    bx lr
84entry:
85  %0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src
86  ret <2 x double> %0
87}
88
89define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
90; CHECK-MVE-LABEL: fabs_float16_t:
91; CHECK-MVE:       @ %bb.0: @ %entry
92; CHECK-MVE-NEXT:    vmovx.f16 s4, s0
93; CHECK-MVE-NEXT:    vabs.f16 s8, s1
94; CHECK-MVE-NEXT:    vabs.f16 s4, s4
95; CHECK-MVE-NEXT:    vmov r0, s4
96; CHECK-MVE-NEXT:    vabs.f16 s4, s0
97; CHECK-MVE-NEXT:    vmov r1, s4
98; CHECK-MVE-NEXT:    vmovx.f16 s0, s3
99; CHECK-MVE-NEXT:    vmov.16 q1[0], r1
100; CHECK-MVE-NEXT:    vabs.f16 s0, s0
101; CHECK-MVE-NEXT:    vmov.16 q1[1], r0
102; CHECK-MVE-NEXT:    vmov r0, s8
103; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
104; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
105; CHECK-MVE-NEXT:    vabs.f16 s8, s8
106; CHECK-MVE-NEXT:    vmov r0, s8
107; CHECK-MVE-NEXT:    vabs.f16 s8, s2
108; CHECK-MVE-NEXT:    vmov.16 q1[3], r0
109; CHECK-MVE-NEXT:    vmov r0, s8
110; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
111; CHECK-MVE-NEXT:    vmov.16 q1[4], r0
112; CHECK-MVE-NEXT:    vabs.f16 s8, s8
113; CHECK-MVE-NEXT:    vmov r0, s8
114; CHECK-MVE-NEXT:    vabs.f16 s8, s3
115; CHECK-MVE-NEXT:    vmov.16 q1[5], r0
116; CHECK-MVE-NEXT:    vmov r0, s8
117; CHECK-MVE-NEXT:    vmov.16 q1[6], r0
118; CHECK-MVE-NEXT:    vmov r0, s0
119; CHECK-MVE-NEXT:    vmov.16 q1[7], r0
120; CHECK-MVE-NEXT:    vmov q0, q1
121; CHECK-MVE-NEXT:    bx lr
122;
123; CHECK-MVEFP-LABEL: fabs_float16_t:
124; CHECK-MVEFP:       @ %bb.0: @ %entry
125; CHECK-MVEFP-NEXT:    vabs.f16 q0, q0
126; CHECK-MVEFP-NEXT:    bx lr
127entry:
128  %0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src)
129  ret <8 x half> %0
130}
131
132define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
133; CHECK-MVE-LABEL: fabs_float32_t:
134; CHECK-MVE:       @ %bb.0: @ %entry
135; CHECK-MVE-NEXT:    vabs.f32 s7, s3
136; CHECK-MVE-NEXT:    vabs.f32 s6, s2
137; CHECK-MVE-NEXT:    vabs.f32 s5, s1
138; CHECK-MVE-NEXT:    vabs.f32 s4, s0
139; CHECK-MVE-NEXT:    vmov q0, q1
140; CHECK-MVE-NEXT:    bx lr
141;
142; CHECK-MVEFP-LABEL: fabs_float32_t:
143; CHECK-MVEFP:       @ %bb.0: @ %entry
144; CHECK-MVEFP-NEXT:    vabs.f32 q0, q0
145; CHECK-MVEFP-NEXT:    bx lr
146entry:
147  %0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src)
148  ret <4 x float> %0
149}
150
151define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) {
152; CHECK-LABEL: fabs_float64_t:
153; CHECK:       @ %bb.0: @ %entry
154; CHECK-NEXT:    vldr d2, .LCPI5_0
155; CHECK-NEXT:    vmov r12, r3, d0
156; CHECK-NEXT:    vmov r0, r1, d2
157; CHECK-NEXT:    vmov r0, r2, d1
158; CHECK-NEXT:    lsrs r1, r1, #31
159; CHECK-NEXT:    bfi r2, r1, #31, #1
160; CHECK-NEXT:    bfi r3, r1, #31, #1
161; CHECK-NEXT:    vmov d1, r0, r2
162; CHECK-NEXT:    vmov d0, r12, r3
163; CHECK-NEXT:    bx lr
164; CHECK-NEXT:    .p2align 3
165; CHECK-NEXT:  @ %bb.1:
166; CHECK-NEXT:  .LCPI5_0:
167; CHECK-NEXT:    .long 0 @ double 0
168; CHECK-NEXT:    .long 0
169entry:
170  %0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src)
171  ret <2 x double> %0
172}
173
174declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
175declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
176declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
177
178