1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __GENWQE_CARD_H__ 20 #define __GENWQE_CARD_H__ 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define GENWQE_DEVNAME "genwqe" 24 #define GENWQE_TYPE_ALTERA_230 0x00 25 #define GENWQE_TYPE_ALTERA_530 0x01 26 #define GENWQE_TYPE_ALTERA_A4 0x02 27 #define GENWQE_TYPE_ALTERA_A7 0x03 28 #define GENWQE_UID_OFFS(uid) ((uid) << 24) 29 #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0) 30 #define GENWQE_HSU_OFFS GENWQE_UID_OFFS(1) 31 #define GENWQE_APP_OFFS GENWQE_UID_OFFS(2) 32 #define GENWQE_MAX_UNITS 3 33 #define IO_EXTENDED_ERROR_POINTER 0x00000048 34 #define IO_ERROR_INJECT_SELECTOR 0x00000060 35 #define IO_EXTENDED_DIAG_SELECTOR 0x00000070 36 #define IO_EXTENDED_DIAG_READ_MBX 0x00000078 37 #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3)) 38 #define GENWQE_EXTENDED_DIAG_SELECTOR(ring,trace) (((ring) << 8) | (trace)) 39 #define IO_SLU_UNITCFG 0x00000000 40 #define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 41 #define IO_SLU_FIR 0x00000008 42 #define IO_SLU_FIR_CLR 0x00000010 43 #define IO_SLU_FEC 0x00000018 44 #define IO_SLU_ERR_ACT_MASK 0x00000020 45 #define IO_SLU_ERR_ATTN_MASK 0x00000028 46 #define IO_SLU_FIRX1_ACT_MASK 0x00000030 47 #define IO_SLU_FIRX0_ACT_MASK 0x00000038 48 #define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040 49 #define IO_SLU_EXTENDED_ERR_PTR 0x00000048 50 #define IO_SLU_COMMON_CONFIG 0x00000060 51 #define IO_SLU_FLASH_FIR 0x00000108 52 #define IO_SLU_SLC_FIR 0x00000110 53 #define IO_SLU_RIU_TRAP 0x00000280 54 #define IO_SLU_FLASH_FEC 0x00000308 55 #define IO_SLU_SLC_FEC 0x00000310 56 #define IO_SLC_QUEUE_SEGMENT 0x00010000 57 #define IO_SLC_VF_QUEUE_SEGMENT 0x00050000 58 #define IO_SLC_QUEUE_OFFSET 0x00010008 59 #define IO_SLC_VF_QUEUE_OFFSET 0x00050008 60 #define IO_SLC_QUEUE_CONFIG 0x00010010 61 #define IO_SLC_VF_QUEUE_CONFIG 0x00050010 62 #define IO_SLC_APPJOB_TIMEOUT 0x00010018 63 #define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018 64 #define TIMEOUT_250MS 0x0000000f 65 #define HEARTBEAT_DISABLE 0x0000ff00 66 #define IO_SLC_QUEUE_INITSQN 0x00010020 67 #define IO_SLC_VF_QUEUE_INITSQN 0x00050020 68 #define IO_SLC_QUEUE_WRAP 0x00010028 69 #define IO_SLC_VF_QUEUE_WRAP 0x00050028 70 #define IO_SLC_QUEUE_STATUS 0x00010100 71 #define IO_SLC_VF_QUEUE_STATUS 0x00050100 72 #define IO_SLC_QUEUE_WTIME 0x00010030 73 #define IO_SLC_VF_QUEUE_WTIME 0x00050030 74 #define IO_SLC_QUEUE_ERRCNTS 0x00010038 75 #define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038 76 #define IO_SLC_QUEUE_LRW 0x00010040 77 #define IO_SLC_VF_QUEUE_LRW 0x00050040 78 #define IO_SLC_FREE_RUNNING_TIMER 0x00010108 79 #define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108 80 #define IO_PF_SLC_VIRTUAL_REGION 0x00050000 81 #define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000 82 #define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8 * (n)) 83 #define IO_SLC_JOBPEND(n) IO_PF_SLC_JOBPEND(n) 84 #define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8 * (n)) 85 #define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8 * (n)) 86 #define IO_SLC_CFGREG_GFIR 0x00020000 87 #define GFIR_ERR_TRIGGER 0x0000ffff 88 #define IO_SLC_CFGREG_SOFTRESET 0x00020018 89 #define IO_SLC_MISC_DEBUG 0x00020060 90 #define IO_SLC_MISC_DEBUG_CLR 0x00020068 91 #define IO_SLC_MISC_DEBUG_SET 0x00020070 92 #define IO_SLU_TEMPERATURE_SENSOR 0x00030000 93 #define IO_SLU_TEMPERATURE_CONFIG 0x00030008 94 #define IO_SLU_VOLTAGE_CONTROL 0x00030080 95 #define IO_SLU_VOLTAGE_NOMINAL 0x00000000 96 #define IO_SLU_VOLTAGE_DOWN5 0x00000006 97 #define IO_SLU_VOLTAGE_UP5 0x00000007 98 #define IO_SLU_LEDCONTROL 0x00030100 99 #define IO_SLU_FLASH_DIRECTACCESS 0x00040010 100 #define IO_SLU_FLASH_DIRECTACCESS2 0x00040020 101 #define IO_SLU_FLASH_CMDINTF 0x00040030 102 #define IO_SLU_BITSTREAM 0x00040040 103 #define IO_HSU_ERR_BEHAVIOR 0x01001010 104 #define IO_SLC2_SQB_TRAP 0x00062000 105 #define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008 106 #define IO_SLC2_FLS_MASTER_TRAP 0x00062010 107 #define IO_HSU_UNITCFG 0x01000000 108 #define IO_HSU_FIR 0x01000008 109 #define IO_HSU_FIR_CLR 0x01000010 110 #define IO_HSU_FEC 0x01000018 111 #define IO_HSU_ERR_ACT_MASK 0x01000020 112 #define IO_HSU_ERR_ATTN_MASK 0x01000028 113 #define IO_HSU_FIRX1_ACT_MASK 0x01000030 114 #define IO_HSU_FIRX0_ACT_MASK 0x01000038 115 #define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040 116 #define IO_HSU_EXTENDED_ERR_PTR 0x01000048 117 #define IO_HSU_COMMON_CONFIG 0x01000060 118 #define IO_APP_UNITCFG 0x02000000 119 #define IO_APP_FIR 0x02000008 120 #define IO_APP_FIR_CLR 0x02000010 121 #define IO_APP_FEC 0x02000018 122 #define IO_APP_ERR_ACT_MASK 0x02000020 123 #define IO_APP_ERR_ATTN_MASK 0x02000028 124 #define IO_APP_FIRX1_ACT_MASK 0x02000030 125 #define IO_APP_FIRX0_ACT_MASK 0x02000038 126 #define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040 127 #define IO_APP_EXTENDED_ERR_PTR 0x02000048 128 #define IO_APP_COMMON_CONFIG 0x02000060 129 #define IO_APP_DEBUG_REG_01 0x02010000 130 #define IO_APP_DEBUG_REG_02 0x02010008 131 #define IO_APP_DEBUG_REG_03 0x02010010 132 #define IO_APP_DEBUG_REG_04 0x02010018 133 #define IO_APP_DEBUG_REG_05 0x02010020 134 #define IO_APP_DEBUG_REG_06 0x02010028 135 #define IO_APP_DEBUG_REG_07 0x02010030 136 #define IO_APP_DEBUG_REG_08 0x02010038 137 #define IO_APP_DEBUG_REG_09 0x02010040 138 #define IO_APP_DEBUG_REG_10 0x02010048 139 #define IO_APP_DEBUG_REG_11 0x02010050 140 #define IO_APP_DEBUG_REG_12 0x02010058 141 #define IO_APP_DEBUG_REG_13 0x02010060 142 #define IO_APP_DEBUG_REG_14 0x02010068 143 #define IO_APP_DEBUG_REG_15 0x02010070 144 #define IO_APP_DEBUG_REG_16 0x02010078 145 #define IO_APP_DEBUG_REG_17 0x02010080 146 #define IO_APP_DEBUG_REG_18 0x02010088 147 struct genwqe_reg_io { 148 __u64 num; 149 __u64 val64; 150 }; 151 #define IO_ILLEGAL_VALUE 0xffffffffffffffffull 152 #define DDCB_ACFUNC_SLU 0x00 153 #define DDCB_ACFUNC_APP 0x01 154 #define DDCB_RETC_IDLE 0x0000 155 #define DDCB_RETC_PENDING 0x0101 156 #define DDCB_RETC_COMPLETE 0x0102 157 #define DDCB_RETC_FAULT 0x0104 158 #define DDCB_RETC_ERROR 0x0108 159 #define DDCB_RETC_FORCED_ERROR 0x01ff 160 #define DDCB_RETC_UNEXEC 0x0110 161 #define DDCB_RETC_TERM 0x0120 162 #define DDCB_RETC_RES0 0x0140 163 #define DDCB_RETC_RES1 0x0180 164 #define DDCB_OPT_ECHO_FORCE_NO 0x0000 165 #define DDCB_OPT_ECHO_FORCE_102 0x0001 166 #define DDCB_OPT_ECHO_FORCE_104 0x0002 167 #define DDCB_OPT_ECHO_FORCE_108 0x0003 168 #define DDCB_OPT_ECHO_FORCE_110 0x0004 169 #define DDCB_OPT_ECHO_FORCE_120 0x0005 170 #define DDCB_OPT_ECHO_FORCE_140 0x0006 171 #define DDCB_OPT_ECHO_FORCE_180 0x0007 172 #define DDCB_OPT_ECHO_COPY_NONE (0 << 5) 173 #define DDCB_OPT_ECHO_COPY_ALL (1 << 5) 174 #define SLCMD_ECHO_SYNC 0x00 175 #define SLCMD_MOVE_FLASH 0x06 176 #define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 177 #define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 178 #define SLCMD_MOVE_FLASH_FLAGS_EMUL 1 179 #define SLCMD_MOVE_FLASH_FLAGS_UPLOAD 2 180 #define SLCMD_MOVE_FLASH_FLAGS_VERIFY 3 181 #define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2) 182 #define SLCMD_MOVE_FLASH_FLAG_POLL (1 << 3) 183 #define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4) 184 #define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5) 185 enum genwqe_card_state { 186 GENWQE_CARD_UNUSED = 0, 187 GENWQE_CARD_USED = 1, 188 GENWQE_CARD_FATAL_ERROR = 2, 189 GENWQE_CARD_RELOAD_BITSTREAM = 3, 190 GENWQE_CARD_STATE_MAX, 191 }; 192 struct genwqe_bitstream { 193 __u64 data_addr; 194 __u32 size; 195 __u32 crc; 196 __u64 target_addr; 197 __u32 partition; 198 __u32 uid; 199 __u64 slu_id; 200 __u64 app_id; 201 __u16 retc; 202 __u16 attn; 203 __u32 progress; 204 }; 205 #define DDCB_LENGTH 256 206 #define DDCB_ASIV_LENGTH 104 207 #define DDCB_ASIV_LENGTH_ATS 96 208 #define DDCB_ASV_LENGTH 64 209 #define DDCB_FIXUPS 12 210 struct genwqe_debug_data { 211 char driver_version[64]; 212 __u64 slu_unitcfg; 213 __u64 app_unitcfg; 214 __u8 ddcb_before[DDCB_LENGTH]; 215 __u8 ddcb_prev[DDCB_LENGTH]; 216 __u8 ddcb_finished[DDCB_LENGTH]; 217 }; 218 #define ATS_TYPE_DATA 0x0ull 219 #define ATS_TYPE_FLAT_RD 0x4ull 220 #define ATS_TYPE_FLAT_RDWR 0x5ull 221 #define ATS_TYPE_SGL_RD 0x6ull 222 #define ATS_TYPE_SGL_RDWR 0x7ull 223 #define ATS_SET_FLAGS(_struct,_field,_flags) (((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8)))) 224 #define ATS_GET_FLAGS(_ats,_byte_offs) (((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf) 225 struct genwqe_ddcb_cmd { 226 __u64 next_addr; 227 __u64 flags; 228 __u8 acfunc; 229 __u8 cmd; 230 __u8 asiv_length; 231 __u8 asv_length; 232 __u16 cmdopts; 233 __u16 retc; 234 __u16 attn; 235 __u16 vcrc; 236 __u32 progress; 237 __u64 deque_ts; 238 __u64 cmplt_ts; 239 __u64 disp_ts; 240 __u64 ddata_addr; 241 __u8 asv[DDCB_ASV_LENGTH]; 242 union { 243 struct { 244 __u64 ats; 245 __u8 asiv[DDCB_ASIV_LENGTH_ATS]; 246 }; 247 __u8 __asiv[DDCB_ASIV_LENGTH]; 248 }; 249 }; 250 #define GENWQE_IOC_CODE 0xa5 251 #define GENWQE_READ_REG64 _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io) 252 #define GENWQE_WRITE_REG64 _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io) 253 #define GENWQE_READ_REG32 _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io) 254 #define GENWQE_WRITE_REG32 _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io) 255 #define GENWQE_READ_REG16 _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io) 256 #define GENWQE_WRITE_REG16 _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io) 257 #define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state) 258 struct genwqe_mem { 259 __u64 addr; 260 __u64 size; 261 __u64 direction; 262 __u64 flags; 263 }; 264 #define GENWQE_PIN_MEM _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem) 265 #define GENWQE_UNPIN_MEM _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem) 266 #define GENWQE_EXECUTE_DDCB _IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd) 267 #define GENWQE_EXECUTE_RAW_DDCB _IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd) 268 #define GENWQE_SLU_UPDATE _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream) 269 #define GENWQE_SLU_READ _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream) 270 #endif 271