1 // Auto-generated file. Do not edit!
2 // Template: src/f32-dwconv/up-avx512.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2019 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/dwconv.h>
15 #include <xnnpack/intrinsics-polyfill.h>
16
17
xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2(size_t channels,size_t output_width,const float ** input,const float * weights,float * output,size_t input_stride,size_t output_increment,size_t input_offset,const float * zero,const union xnn_f32_minmax_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2(
19 size_t channels,
20 size_t output_width,
21 const float** input,
22 const float* weights,
23 float* output,
24 size_t input_stride,
25 size_t output_increment,
26 size_t input_offset,
27 const float* zero,
28 const union xnn_f32_minmax_params params[restrict XNN_MIN_ELEMENTS(1)])
29 {
30 assert(channels != 0);
31 assert(output_width != 0);
32
33 const __m512 vmax = _mm512_broadcast_f32x4(_mm_load_ps(params->sse.max));
34 const __m512 vmin = _mm512_broadcast_f32x4(_mm_load_ps(params->sse.min));
35 do {
36 const float* i0 = input[0];
37 assert(i0 != NULL);
38 if XNN_UNPREDICTABLE(i0 != zero) {
39 i0 = (const float*) ((uintptr_t) i0 + input_offset);
40 }
41 const float* i1 = input[1];
42 assert(i1 != NULL);
43 if XNN_UNPREDICTABLE(i1 != zero) {
44 i1 = (const float*) ((uintptr_t) i1 + input_offset);
45 }
46 const float* i2 = input[2];
47 assert(i2 != NULL);
48 if XNN_UNPREDICTABLE(i2 != zero) {
49 i2 = (const float*) ((uintptr_t) i2 + input_offset);
50 }
51 const float* i3 = input[3];
52 assert(i3 != NULL);
53 if XNN_UNPREDICTABLE(i3 != zero) {
54 i3 = (const float*) ((uintptr_t) i3 + input_offset);
55 }
56 input = (const float**) ((uintptr_t) input + input_stride);
57
58 size_t c = channels;
59 const float* w = weights;
60 for (; c >= 16; c -= 16) {
61 __m512 vacc0123456789ABCDEFp0 = _mm512_load_ps(w);
62
63
64 const __m512 vi0x0123456789ABCDEF = _mm512_loadu_ps(i0);
65 i0 += 16;
66
67 const __m512 vk0x0123456789ABCDEF = _mm512_load_ps(w + 16);
68 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi0x0123456789ABCDEF, vk0x0123456789ABCDEF, vacc0123456789ABCDEFp0);
69
70 const __m512 vi1x0123456789ABCDEF = _mm512_loadu_ps(i1);
71 i1 += 16;
72
73 const __m512 vk1x0123456789ABCDEF = _mm512_load_ps(w + 32);
74 __m512 vacc0123456789ABCDEFp1 = _mm512_mul_ps(vi1x0123456789ABCDEF, vk1x0123456789ABCDEF);
75
76 const __m512 vi2x0123456789ABCDEF = _mm512_loadu_ps(i2);
77 i2 += 16;
78
79 const __m512 vk2x0123456789ABCDEF = _mm512_load_ps(w + 48);
80 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi2x0123456789ABCDEF, vk2x0123456789ABCDEF, vacc0123456789ABCDEFp0);
81
82 const __m512 vi3x0123456789ABCDEF = _mm512_loadu_ps(i3);
83 i3 += 16;
84
85 const __m512 vk3x0123456789ABCDEF = _mm512_load_ps(w + 64);
86 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi3x0123456789ABCDEF, vk3x0123456789ABCDEF, vacc0123456789ABCDEFp1);
87
88 w += 80;
89
90 // Add up all accumulators to vacc0123456789ABCDEFp0
91 vacc0123456789ABCDEFp0 = _mm512_add_ps(vacc0123456789ABCDEFp0, vacc0123456789ABCDEFp1);
92
93 __m512 vacc0123456789ABCDEF = _mm512_max_ps(vacc0123456789ABCDEFp0, vmin);
94 vacc0123456789ABCDEF = _mm512_min_ps(vacc0123456789ABCDEF, vmax);
95
96 _mm512_storeu_ps(output, vacc0123456789ABCDEF);
97 output += 16;
98 }
99 if XNN_UNLIKELY(c != 0) {
100 assert(c >= 1);
101 assert(c <= 16);
102 // Prepare mask for valid 32-bit elements (depends on nc).
103 const __mmask16 vmask = _cvtu32_mask16((uint16_t) ((uint32_t) (UINT32_C(1) << c) - UINT32_C(1)));
104
105 __m512 vacc0123456789ABCDEFp0 = _mm512_maskz_loadu_ps(vmask, w);
106
107 const __m512 vi0x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i0);
108 const __m512 vk0x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 16);
109 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi0x0123456789ABCDEF, vk0x0123456789ABCDEF, vacc0123456789ABCDEFp0);
110
111 const __m512 vi1x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i1);
112 const __m512 vk1x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 32);
113 __m512 vacc0123456789ABCDEFp1 = _mm512_mul_ps(vi1x0123456789ABCDEF, vk1x0123456789ABCDEF);
114
115 const __m512 vi2x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i2);
116 const __m512 vk2x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 48);
117 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi2x0123456789ABCDEF, vk2x0123456789ABCDEF, vacc0123456789ABCDEFp0);
118
119 const __m512 vi3x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i3);
120 const __m512 vk3x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 64);
121 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi3x0123456789ABCDEF, vk3x0123456789ABCDEF, vacc0123456789ABCDEFp1);
122
123 // Add up all accumulators to vacc0123456789ABCDEFp0
124 vacc0123456789ABCDEFp0 = _mm512_add_ps(vacc0123456789ABCDEFp0, vacc0123456789ABCDEFp1);
125
126 __m512 vacc0123456789ABCDEF = _mm512_max_ps(vacc0123456789ABCDEFp0, vmin);
127 vacc0123456789ABCDEF = _mm512_min_ps(vacc0123456789ABCDEF, vmax);
128
129 _mm512_mask_storeu_ps(output, vmask, vacc0123456789ABCDEF);
130 output += c;
131 }
132
133 output = (float*) ((uintptr_t) output + output_increment);
134 } while (--output_width != 0);
135 }
136