1 // Auto-generated file. Do not edit!
2 // Template: src/f32-dwconv/up-avx512.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2019 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/dwconv.h>
15 #include <xnnpack/intrinsics-polyfill.h>
16
17
xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2(size_t channels,size_t output_width,const float ** input,const float * weights,float * output,size_t input_stride,size_t output_increment,size_t input_offset,const float * zero,const union xnn_f32_minmax_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2(
19 size_t channels,
20 size_t output_width,
21 const float** input,
22 const float* weights,
23 float* output,
24 size_t input_stride,
25 size_t output_increment,
26 size_t input_offset,
27 const float* zero,
28 const union xnn_f32_minmax_params params[restrict XNN_MIN_ELEMENTS(1)])
29 {
30 assert(channels != 0);
31 assert(output_width != 0);
32
33 const __m512 vmax = _mm512_broadcast_f32x4(_mm_load_ps(params->sse.max));
34 const __m512 vmin = _mm512_broadcast_f32x4(_mm_load_ps(params->sse.min));
35 do {
36 const float* i0 = input[0];
37 assert(i0 != NULL);
38 if XNN_UNPREDICTABLE(i0 != zero) {
39 i0 = (const float*) ((uintptr_t) i0 + input_offset);
40 }
41 const float* i1 = input[1];
42 assert(i1 != NULL);
43 if XNN_UNPREDICTABLE(i1 != zero) {
44 i1 = (const float*) ((uintptr_t) i1 + input_offset);
45 }
46 const float* i2 = input[2];
47 assert(i2 != NULL);
48 if XNN_UNPREDICTABLE(i2 != zero) {
49 i2 = (const float*) ((uintptr_t) i2 + input_offset);
50 }
51 const float* i3 = input[3];
52 assert(i3 != NULL);
53 if XNN_UNPREDICTABLE(i3 != zero) {
54 i3 = (const float*) ((uintptr_t) i3 + input_offset);
55 }
56 const float* i4 = input[4];
57 assert(i4 != NULL);
58 if XNN_UNPREDICTABLE(i4 != zero) {
59 i4 = (const float*) ((uintptr_t) i4 + input_offset);
60 }
61 const float* i5 = input[5];
62 assert(i5 != NULL);
63 if XNN_UNPREDICTABLE(i5 != zero) {
64 i5 = (const float*) ((uintptr_t) i5 + input_offset);
65 }
66 const float* i6 = input[6];
67 assert(i6 != NULL);
68 if XNN_UNPREDICTABLE(i6 != zero) {
69 i6 = (const float*) ((uintptr_t) i6 + input_offset);
70 }
71 const float* i7 = input[7];
72 assert(i7 != NULL);
73 if XNN_UNPREDICTABLE(i7 != zero) {
74 i7 = (const float*) ((uintptr_t) i7 + input_offset);
75 }
76 const float* i8 = input[8];
77 assert(i8 != NULL);
78 if XNN_UNPREDICTABLE(i8 != zero) {
79 i8 = (const float*) ((uintptr_t) i8 + input_offset);
80 }
81 input = (const float**) ((uintptr_t) input + input_stride);
82
83 size_t c = channels;
84 const float* w = weights;
85 for (; c >= 16; c -= 16) {
86 __m512 vacc0123456789ABCDEFp0 = _mm512_load_ps(w);
87
88
89 const __m512 vi0x0123456789ABCDEF = _mm512_loadu_ps(i0);
90 i0 += 16;
91
92 const __m512 vk0x0123456789ABCDEF = _mm512_load_ps(w + 16);
93 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi0x0123456789ABCDEF, vk0x0123456789ABCDEF, vacc0123456789ABCDEFp0);
94
95 const __m512 vi1x0123456789ABCDEF = _mm512_loadu_ps(i1);
96 i1 += 16;
97
98 const __m512 vk1x0123456789ABCDEF = _mm512_load_ps(w + 32);
99 __m512 vacc0123456789ABCDEFp1 = _mm512_mul_ps(vi1x0123456789ABCDEF, vk1x0123456789ABCDEF);
100
101 const __m512 vi2x0123456789ABCDEF = _mm512_loadu_ps(i2);
102 i2 += 16;
103
104 const __m512 vk2x0123456789ABCDEF = _mm512_load_ps(w + 48);
105 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi2x0123456789ABCDEF, vk2x0123456789ABCDEF, vacc0123456789ABCDEFp0);
106
107 const __m512 vi3x0123456789ABCDEF = _mm512_loadu_ps(i3);
108 i3 += 16;
109
110 const __m512 vk3x0123456789ABCDEF = _mm512_load_ps(w + 64);
111 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi3x0123456789ABCDEF, vk3x0123456789ABCDEF, vacc0123456789ABCDEFp1);
112
113 const __m512 vi4x0123456789ABCDEF = _mm512_loadu_ps(i4);
114 i4 += 16;
115
116 const __m512 vk4x0123456789ABCDEF = _mm512_load_ps(w + 80);
117 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi4x0123456789ABCDEF, vk4x0123456789ABCDEF, vacc0123456789ABCDEFp0);
118
119 const __m512 vi5x0123456789ABCDEF = _mm512_loadu_ps(i5);
120 i5 += 16;
121
122 const __m512 vk5x0123456789ABCDEF = _mm512_load_ps(w + 96);
123 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi5x0123456789ABCDEF, vk5x0123456789ABCDEF, vacc0123456789ABCDEFp1);
124
125 const __m512 vi6x0123456789ABCDEF = _mm512_loadu_ps(i6);
126 i6 += 16;
127
128 const __m512 vk6x0123456789ABCDEF = _mm512_load_ps(w + 112);
129 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi6x0123456789ABCDEF, vk6x0123456789ABCDEF, vacc0123456789ABCDEFp0);
130
131 const __m512 vi7x0123456789ABCDEF = _mm512_loadu_ps(i7);
132 i7 += 16;
133
134 const __m512 vk7x0123456789ABCDEF = _mm512_load_ps(w + 128);
135 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi7x0123456789ABCDEF, vk7x0123456789ABCDEF, vacc0123456789ABCDEFp1);
136
137 const __m512 vi8x0123456789ABCDEF = _mm512_loadu_ps(i8);
138 i8 += 16;
139
140 const __m512 vk8x0123456789ABCDEF = _mm512_load_ps(w + 144);
141 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi8x0123456789ABCDEF, vk8x0123456789ABCDEF, vacc0123456789ABCDEFp0);
142
143 w += 160;
144
145 // Add up all accumulators to vacc0123456789ABCDEFp0
146 vacc0123456789ABCDEFp0 = _mm512_add_ps(vacc0123456789ABCDEFp0, vacc0123456789ABCDEFp1);
147
148 __m512 vacc0123456789ABCDEF = _mm512_max_ps(vacc0123456789ABCDEFp0, vmin);
149 vacc0123456789ABCDEF = _mm512_min_ps(vacc0123456789ABCDEF, vmax);
150
151 _mm512_storeu_ps(output, vacc0123456789ABCDEF);
152 output += 16;
153 }
154 if XNN_UNLIKELY(c != 0) {
155 assert(c >= 1);
156 assert(c <= 16);
157 // Prepare mask for valid 32-bit elements (depends on nc).
158 const __mmask16 vmask = _cvtu32_mask16((uint16_t) ((uint32_t) (UINT32_C(1) << c) - UINT32_C(1)));
159
160 __m512 vacc0123456789ABCDEFp0 = _mm512_maskz_loadu_ps(vmask, w);
161
162 const __m512 vi0x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i0);
163 const __m512 vk0x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 16);
164 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi0x0123456789ABCDEF, vk0x0123456789ABCDEF, vacc0123456789ABCDEFp0);
165
166 const __m512 vi1x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i1);
167 const __m512 vk1x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 32);
168 __m512 vacc0123456789ABCDEFp1 = _mm512_mul_ps(vi1x0123456789ABCDEF, vk1x0123456789ABCDEF);
169
170 const __m512 vi2x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i2);
171 const __m512 vk2x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 48);
172 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi2x0123456789ABCDEF, vk2x0123456789ABCDEF, vacc0123456789ABCDEFp0);
173
174 const __m512 vi3x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i3);
175 const __m512 vk3x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 64);
176 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi3x0123456789ABCDEF, vk3x0123456789ABCDEF, vacc0123456789ABCDEFp1);
177
178 const __m512 vi4x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i4);
179 const __m512 vk4x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 80);
180 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi4x0123456789ABCDEF, vk4x0123456789ABCDEF, vacc0123456789ABCDEFp0);
181
182 const __m512 vi5x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i5);
183 const __m512 vk5x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 96);
184 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi5x0123456789ABCDEF, vk5x0123456789ABCDEF, vacc0123456789ABCDEFp1);
185
186 const __m512 vi6x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i6);
187 const __m512 vk6x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 112);
188 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi6x0123456789ABCDEF, vk6x0123456789ABCDEF, vacc0123456789ABCDEFp0);
189
190 const __m512 vi7x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i7);
191 const __m512 vk7x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 128);
192 vacc0123456789ABCDEFp1 = _mm512_fmadd_ps(vi7x0123456789ABCDEF, vk7x0123456789ABCDEF, vacc0123456789ABCDEFp1);
193
194 const __m512 vi8x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, i8);
195 const __m512 vk8x0123456789ABCDEF = _mm512_maskz_loadu_ps(vmask, w + 144);
196 vacc0123456789ABCDEFp0 = _mm512_fmadd_ps(vi8x0123456789ABCDEF, vk8x0123456789ABCDEF, vacc0123456789ABCDEFp0);
197
198 // Add up all accumulators to vacc0123456789ABCDEFp0
199 vacc0123456789ABCDEFp0 = _mm512_add_ps(vacc0123456789ABCDEFp0, vacc0123456789ABCDEFp1);
200
201 __m512 vacc0123456789ABCDEF = _mm512_max_ps(vacc0123456789ABCDEFp0, vmin);
202 vacc0123456789ABCDEF = _mm512_min_ps(vacc0123456789ABCDEF, vmax);
203
204 _mm512_mask_storeu_ps(output, vmask, vacc0123456789ABCDEF);
205 output += c;
206 }
207
208 output = (float*) ((uintptr_t) output + output_increment);
209 } while (--output_width != 0);
210 }
211