1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x4(size_t elements,const float * input,float * output,float * sum,float max)18 void xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x4(
19 size_t elements,
20 const float* input,
21 float* output,
22 float* sum,
23 float max) XNN_DISABLE_TSAN
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
28 // The smallest x for which expf(x) is normalized.
29 const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep6f);
30 const float32x4_t vlog2e = vmovq_n_f32(0x1.715476p+0f);
31 // Last 7 bits are zeroes
32 const float32x4_t vminus_ln2_hi = vmovq_n_f32(-0x1.62E400p-1f);
33 const float32x4_t vminus_ln2_lo = vmovq_n_f32(-0x1.7F7D1Cp-20f);
34
35 const float32x4_t vc1 = vmovq_n_f32(0x1.FFFFF6p-1f);
36 const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
37 const float32x4_t vc3 = vmovq_n_f32(0x1.555A80p-3f);
38 const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
39 const float32x4_t vc5 = vmovq_n_f32(0x1.0F9F9Cp-7f);
40
41 const float32x4_t vi_max = vdupq_n_f32(max);
42
43 float32x4_t vacc = vmovq_n_f32(0.0f);
44 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
45 // Load 4 inputs at a time.
46 const float32x4_t vi = vld1q_f32(input); input += 4;
47
48 // Subtract maximum input x := i - i_max. This implies x <= 0.
49 const float32x4_t vx = vsubq_f32(vi, vi_max);
50
51 // Compute reduced argument n := round(x / log(2)).
52 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
53 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
54 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
55 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
56 // of the algorithm.
57 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
58
59 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
60 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
61 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
62
63 // Subtract the large number back to get final n := round(x / log(2)).
64 vn = vsubq_f32(vn, vmagic_bias);
65
66 // Compute reduced argument t := z - n * log(2).
67 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
68 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
69 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
70
71 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
72 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
73 vp = vmlaq_f32(vc3, vp, vt);
74 vp = vmlaq_f32(vc2, vp, vt);
75 vp = vmlaq_f32(vc1, vp, vt);
76
77 // Reconstruct the final f value:
78 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
79 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
80 // = s + (t * s) * p
81 vt = vmulq_f32(vt, vs);
82 float32x4_t vf = vmlaq_f32(vs, vp, vt);
83
84 // For inputs below denormal cutoff, replace output with +0.0f.
85 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
86 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
87
88 // Store 4 outputs at a time.
89 vst1q_f32(output, vf); output += 4;
90
91 // Accumulate computed exponents.
92 vacc = vaddq_f32(vacc, vf);
93 }
94 #if XNN_ARCH_ARM64
95 float vacc_lo = vaddvq_f32(vacc);
96 #else
97 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
98 #endif
99 if (elements != 0) {
100 assert(elements >= 1 * sizeof(float));
101 assert(elements <= 3 * sizeof(float));
102 // Load 4 inputs at a time.
103 const float32x4_t vi = vld1q_f32(input); input += 4;
104
105 // Subtract maximum input x := i - i_max. This implies x <= 0.
106 const float32x4_t vx = vsubq_f32(vi, vi_max);
107
108 // Compute reduced argument n := round(x / log(2)).
109 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
110 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
111 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
112 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
113 // of the algorithm.
114 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
115
116 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
117 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
118 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
119
120 // Subtract the large number back to get final n := round(x / log(2)).
121 vn = vsubq_f32(vn, vmagic_bias);
122
123 // Compute reduced argument t := z - n * log(2).
124 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
125 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
126 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
127
128 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
129 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
130 vp = vmlaq_f32(vc3, vp, vt);
131 vp = vmlaq_f32(vc2, vp, vt);
132 vp = vmlaq_f32(vc1, vp, vt);
133
134 // Reconstruct the final f value:
135 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
136 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
137 // = s + (t * s) * p
138 vt = vmulq_f32(vt, vs);
139 float32x4_t vf = vmlaq_f32(vs, vp, vt);
140
141 // For inputs below denormal cutoff, replace output with +0.0f.
142 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
143 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
144
145 float32x2_t vf_lo = vget_low_f32(vf);
146 if (elements & (2 * sizeof(float))) {
147 // Store 2 outputs at a time.
148 vst1_f32(output, vf_lo); output += 2;
149
150 // Accumulate 2 computed exponents.
151 #if XNN_ARCH_ARM64
152 vacc_lo += vaddv_f32(vf_lo);
153 #else
154 vacc_lo = vadd_f32(vacc_lo, vf_lo);
155 #endif
156
157 vf_lo = vget_high_f32(vf);
158 }
159 if (elements & (1 * sizeof(float))) {
160 // Store 1 output at a time.
161 vst1_lane_f32(output, vf_lo, 0);
162
163 // Accumulate 1 computed exponent.
164 #if XNN_ARCH_ARM64
165 vacc_lo += vget_lane_f32(vf_lo, 0);
166 #else
167 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
168 #endif
169 }
170 }
171 // Reduce 4 elements in the SIMD register
172 #if XNN_ARCH_ARM64
173 *sum = vacc_lo;
174 #else
175 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
176 #endif
177 }
178