1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8(size_t elements,const float * input,float * output,float * sum,float max)18 void xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8(
19 size_t elements,
20 const float* input,
21 float* output,
22 float* sum,
23 float max) XNN_DISABLE_TSAN
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
28 // The smallest x for which expf(x) is normalized.
29 const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep6f);
30 const float32x4_t vlog2e = vmovq_n_f32(0x1.715476p+0f);
31 const float32x4_t vminus_ln2_hi = vmovq_n_f32(-0x1.62E43p-1f);
32 const float32x4_t vminus_ln2_lo = vmovq_n_f32(0x1.05C61p-29f);
33
34 const float32x4_t vc1 = vmovq_n_f32(0x1.FFFFF6p-1f);
35 const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
36 const float32x4_t vc3 = vmovq_n_f32(0x1.555A80p-3f);
37 const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
38 const float32x4_t vc5 = vmovq_n_f32(0x1.0F9F9Cp-7f);
39
40 const float32x4_t vi_max = vdupq_n_f32(max);
41
42 float32x4_t vacc0 = vmovq_n_f32(0.0f);
43 for (; elements >= 8 * sizeof(float); elements -= 8 * sizeof(float)) {
44 // Load 8 (2x4) inputs at a time.
45 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
46 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
47
48 // Subtract maximum input x := i - i_max. This implies x <= 0.
49 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
50 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
51
52 // Compute reduced argument n := round(x / log(2)).
53 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
54 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
55 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
56 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
57 // of the algorithm.
58 float32x4_t vn0123 = vfmaq_f32(vmagic_bias, vx0123, vlog2e);
59 float32x4_t vn4567 = vfmaq_f32(vmagic_bias, vx4567, vlog2e);
60
61 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
62 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
63 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
64 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
65
66 // Subtract the large number back to get final n := round(x / log(2)).
67 vn0123 = vsubq_f32(vn0123, vmagic_bias);
68 vn4567 = vsubq_f32(vn4567, vmagic_bias);
69
70 // Compute reduced argument t := z - n * log(2).
71 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
72 float32x4_t vt0123 = vfmaq_f32(vx0123, vn0123, vminus_ln2_hi);
73 float32x4_t vt4567 = vfmaq_f32(vx4567, vn4567, vminus_ln2_hi);
74
75 vt0123 = vfmaq_f32(vt0123, vn0123, vminus_ln2_lo);
76 vt4567 = vfmaq_f32(vt4567, vn4567, vminus_ln2_lo);
77
78 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
79 float32x4_t vp0123 = vfmaq_f32(vc4, vc5, vt0123);
80 float32x4_t vp4567 = vfmaq_f32(vc4, vc5, vt4567);
81
82 vp0123 = vfmaq_f32(vc3, vp0123, vt0123);
83 vp4567 = vfmaq_f32(vc3, vp4567, vt4567);
84
85 vp0123 = vfmaq_f32(vc2, vp0123, vt0123);
86 vp4567 = vfmaq_f32(vc2, vp4567, vt4567);
87
88 vp0123 = vfmaq_f32(vc1, vp0123, vt0123);
89 vp4567 = vfmaq_f32(vc1, vp4567, vt4567);
90
91 // Reconstruct the final f value:
92 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
93 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
94 // = s + (t * s) * p
95 vt0123 = vmulq_f32(vt0123, vs0123);
96 vt4567 = vmulq_f32(vt4567, vs4567);
97
98 float32x4_t vf0123 = vfmaq_f32(vs0123, vp0123, vt0123);
99 float32x4_t vf4567 = vfmaq_f32(vs4567, vp4567, vt4567);
100
101 // For inputs below denormal cutoff, replace output with +0.0f.
102 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
103 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
104 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
105
106 // Store 8 (2x4) outputs at a time.
107 vst1q_f32(output, vf0123); output += 4;
108 vst1q_f32(output, vf4567); output += 4;
109
110 // Accumulate computed exponents.
111 vacc0 = vaddq_f32(vacc0, vf0123);
112 vacc0 = vaddq_f32(vacc0, vf4567);
113 }
114
115 float32x4_t vacc = vacc0;
116 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
117 // Load 4 inputs at a time.
118 const float32x4_t vi = vld1q_f32(input); input += 4;
119
120 // Subtract maximum input x := i - i_max. This implies x <= 0.
121 const float32x4_t vx = vsubq_f32(vi, vi_max);
122
123 // Compute reduced argument n := round(x / log(2)).
124 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
125 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
126 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
127 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
128 // of the algorithm.
129 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
130
131 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
132 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
133 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
134
135 // Subtract the large number back to get final n := round(x / log(2)).
136 vn = vsubq_f32(vn, vmagic_bias);
137
138 // Compute reduced argument t := z - n * log(2).
139 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
140 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2_hi);
141 vt = vfmaq_f32(vt, vn, vminus_ln2_lo);
142
143 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
144 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
145 vp = vfmaq_f32(vc3, vp, vt);
146 vp = vfmaq_f32(vc2, vp, vt);
147 vp = vfmaq_f32(vc1, vp, vt);
148
149 // Reconstruct the final f value:
150 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
151 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
152 // = s + (t * s) * p
153 vt = vmulq_f32(vt, vs);
154 float32x4_t vf = vfmaq_f32(vs, vp, vt);
155
156 // For inputs below denormal cutoff, replace output with +0.0f.
157 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
158 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
159
160 // Store 4 outputs at a time.
161 vst1q_f32(output, vf); output += 4;
162
163 // Accumulate computed exponents.
164 vacc = vaddq_f32(vacc, vf);
165 }
166 #if XNN_ARCH_ARM64
167 float vacc_lo = vaddvq_f32(vacc);
168 #else
169 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
170 #endif
171 if (elements != 0) {
172 assert(elements >= 1 * sizeof(float));
173 assert(elements <= 3 * sizeof(float));
174 // Load 4 inputs at a time.
175 const float32x4_t vi = vld1q_f32(input); input += 4;
176
177 // Subtract maximum input x := i - i_max. This implies x <= 0.
178 const float32x4_t vx = vsubq_f32(vi, vi_max);
179
180 // Compute reduced argument n := round(x / log(2)).
181 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
182 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
183 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
184 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
185 // of the algorithm.
186 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
187
188 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
189 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
190 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
191
192 // Subtract the large number back to get final n := round(x / log(2)).
193 vn = vsubq_f32(vn, vmagic_bias);
194
195 // Compute reduced argument t := z - n * log(2).
196 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
197 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2_hi);
198 vt = vfmaq_f32(vt, vn, vminus_ln2_lo);
199
200 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
201 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
202 vp = vfmaq_f32(vc3, vp, vt);
203 vp = vfmaq_f32(vc2, vp, vt);
204 vp = vfmaq_f32(vc1, vp, vt);
205
206 // Reconstruct the final f value:
207 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
208 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
209 // = s + (t * s) * p
210 vt = vmulq_f32(vt, vs);
211 float32x4_t vf = vfmaq_f32(vs, vp, vt);
212
213 // For inputs below denormal cutoff, replace output with +0.0f.
214 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
215 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
216
217 float32x2_t vf_lo = vget_low_f32(vf);
218 if (elements & (2 * sizeof(float))) {
219 // Store 2 outputs at a time.
220 vst1_f32(output, vf_lo); output += 2;
221
222 // Accumulate 2 computed exponents.
223 #if XNN_ARCH_ARM64
224 vacc_lo += vaddv_f32(vf_lo);
225 #else
226 vacc_lo = vadd_f32(vacc_lo, vf_lo);
227 #endif
228
229 vf_lo = vget_high_f32(vf);
230 }
231 if (elements & (1 * sizeof(float))) {
232 // Store 1 output at a time.
233 vst1_lane_f32(output, vf_lo, 0);
234
235 // Accumulate 1 computed exponent.
236 #if XNN_ARCH_ARM64
237 vacc_lo += vget_lane_f32(vf_lo, 0);
238 #else
239 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
240 #endif
241 }
242 }
243 // Reduce 4 elements in the SIMD register
244 #if XNN_ARCH_ARM64
245 *sum = vacc_lo;
246 #else
247 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
248 #endif
249 }
250