1 // Copyright 2019 Google LLC
2 //
3 // This source code is licensed under the BSD-style license found in the
4 // LICENSE file in the root directory of this source tree.
5 //
6 // Auto-generated file. Do not edit!
7 //   Specification: test/f16-vmulcaddc-minmax.yaml
8 //   Generator: tools/generate-vmulcaddc-test.py
9 
10 
11 #include <gtest/gtest.h>
12 
13 #include <xnnpack/common.h>
14 #include <xnnpack/isa-checks.h>
15 
16 #include <xnnpack/vmulcaddc.h>
17 #include "vmulcaddc-microkernel-tester.h"
18 
19 
20 #if XNN_ARCH_ARM64
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,channels_eq_8)21   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, channels_eq_8) {
22     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
23     VMulCAddCMicrokernelTester()
24       .channel_tile(8)
25       .channels(8)
26       .rows(2)
27       .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
28   }
29 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,channels_div_8)30   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, channels_div_8) {
31     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
32     for (size_t channels = 16; channels < 80; channels += 8) {
33       VMulCAddCMicrokernelTester()
34         .channel_tile(8)
35         .channels(channels)
36         .rows(2)
37         .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
38     }
39   }
40 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,channels_lt_8)41   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, channels_lt_8) {
42     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
43     for (size_t channels = 1; channels < 8; channels++) {
44       VMulCAddCMicrokernelTester()
45         .channel_tile(8)
46         .channels(channels)
47         .rows(2)
48         .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
49     }
50   }
51 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,channels_gt_8)52   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, channels_gt_8) {
53     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
54     for (size_t channels = 9; channels < 16; channels++) {
55       VMulCAddCMicrokernelTester()
56         .channel_tile(8)
57         .channels(channels)
58         .rows(2)
59         .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
60     }
61   }
62 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,rows_lt_2)63   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, rows_lt_2) {
64     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
65     for (size_t rows = 1; rows < 2; rows++) {
66       for (size_t channels = 1; channels <= 40; channels += 7) {
67         VMulCAddCMicrokernelTester()
68           .channel_tile(8)
69           .channels(channels)
70           .rows(rows)
71           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
72       }
73     }
74   }
75 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,rows_div_2)76   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, rows_div_2) {
77     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
78     for (size_t rows = 4; rows <= 8; rows += 2) {
79       for (size_t channels = 1; channels <= 40; channels += 7) {
80         VMulCAddCMicrokernelTester()
81           .channel_tile(8)
82           .channels(channels)
83           .rows(rows)
84           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
85       }
86     }
87   }
88 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,rows_gt_2)89   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, rows_gt_2) {
90     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
91     for (size_t rows = 3; rows < 4; rows++) {
92       for (size_t channels = 1; channels <= 40; channels += 7) {
93         VMulCAddCMicrokernelTester()
94           .channel_tile(8)
95           .channels(channels)
96           .rows(rows)
97           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
98       }
99     }
100   }
101 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,input_stride)102   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, input_stride) {
103     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
104     for (size_t rows = 1; rows <= 6; rows += 1) {
105       for (size_t channels = 1; channels <= 40; channels += 7) {
106         VMulCAddCMicrokernelTester()
107           .channel_tile(8)
108           .channels(channels)
109           .rows(rows)
110           .input_stride(43)
111           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
112       }
113     }
114   }
115 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,output_stride)116   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, output_stride) {
117     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
118     for (size_t rows = 1; rows <= 6; rows += 1) {
119       for (size_t channels = 1; channels <= 40; channels += 7) {
120         VMulCAddCMicrokernelTester()
121           .channel_tile(8)
122           .channels(channels)
123           .rows(rows)
124           .output_stride(43)
125           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
126       }
127     }
128   }
129 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,inplace)130   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, inplace) {
131     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
132     for (size_t rows = 1; rows <= 6; rows += 1) {
133       for (size_t channels = 1; channels <= 40; channels += 7) {
134         VMulCAddCMicrokernelTester()
135           .channel_tile(8)
136           .channels(channels)
137           .rows(rows)
138           .inplace(true)
139           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
140       }
141     }
142   }
143 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,qmin)144   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, qmin) {
145     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
146     for (size_t rows = 1; rows <= 6; rows += 1) {
147       for (size_t channels = 1; channels <= 40; channels += 7) {
148         VMulCAddCMicrokernelTester()
149           .channel_tile(8)
150           .channels(channels)
151           .rows(rows)
152           .qmin(128)
153           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
154       }
155     }
156   }
157 
TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X,qmax)158   TEST(F16_VMULCADDC_MINMAX_C8__NEONFP16ARITH_2X, qmax) {
159     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
160     for (size_t rows = 1; rows <= 6; rows += 1) {
161       for (size_t channels = 1; channels <= 40; channels += 7) {
162         VMulCAddCMicrokernelTester()
163           .channel_tile(8)
164           .channels(channels)
165           .rows(rows)
166           .qmax(128)
167           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x);
168       }
169     }
170   }
171 #endif  // XNN_ARCH_ARM64
172 
173 
174 #if XNN_ARCH_ARM64
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,channels_eq_16)175   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, channels_eq_16) {
176     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
177     VMulCAddCMicrokernelTester()
178       .channel_tile(16)
179       .channels(16)
180       .rows(2)
181       .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
182   }
183 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,channels_div_16)184   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, channels_div_16) {
185     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
186     for (size_t channels = 32; channels < 160; channels += 16) {
187       VMulCAddCMicrokernelTester()
188         .channel_tile(16)
189         .channels(channels)
190         .rows(2)
191         .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
192     }
193   }
194 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,channels_lt_16)195   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, channels_lt_16) {
196     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
197     for (size_t channels = 1; channels < 16; channels++) {
198       VMulCAddCMicrokernelTester()
199         .channel_tile(16)
200         .channels(channels)
201         .rows(2)
202         .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
203     }
204   }
205 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,channels_gt_16)206   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, channels_gt_16) {
207     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
208     for (size_t channels = 17; channels < 32; channels++) {
209       VMulCAddCMicrokernelTester()
210         .channel_tile(16)
211         .channels(channels)
212         .rows(2)
213         .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
214     }
215   }
216 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,rows_lt_2)217   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, rows_lt_2) {
218     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
219     for (size_t rows = 1; rows < 2; rows++) {
220       for (size_t channels = 1; channels <= 80; channels += 15) {
221         VMulCAddCMicrokernelTester()
222           .channel_tile(16)
223           .channels(channels)
224           .rows(rows)
225           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
226       }
227     }
228   }
229 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,rows_div_2)230   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, rows_div_2) {
231     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
232     for (size_t rows = 4; rows <= 8; rows += 2) {
233       for (size_t channels = 1; channels <= 80; channels += 15) {
234         VMulCAddCMicrokernelTester()
235           .channel_tile(16)
236           .channels(channels)
237           .rows(rows)
238           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
239       }
240     }
241   }
242 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,rows_gt_2)243   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, rows_gt_2) {
244     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
245     for (size_t rows = 3; rows < 4; rows++) {
246       for (size_t channels = 1; channels <= 80; channels += 15) {
247         VMulCAddCMicrokernelTester()
248           .channel_tile(16)
249           .channels(channels)
250           .rows(rows)
251           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
252       }
253     }
254   }
255 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,input_stride)256   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, input_stride) {
257     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
258     for (size_t rows = 1; rows <= 6; rows += 1) {
259       for (size_t channels = 1; channels <= 80; channels += 15) {
260         VMulCAddCMicrokernelTester()
261           .channel_tile(16)
262           .channels(channels)
263           .rows(rows)
264           .input_stride(83)
265           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
266       }
267     }
268   }
269 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,output_stride)270   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, output_stride) {
271     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
272     for (size_t rows = 1; rows <= 6; rows += 1) {
273       for (size_t channels = 1; channels <= 80; channels += 15) {
274         VMulCAddCMicrokernelTester()
275           .channel_tile(16)
276           .channels(channels)
277           .rows(rows)
278           .output_stride(83)
279           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
280       }
281     }
282   }
283 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,inplace)284   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, inplace) {
285     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
286     for (size_t rows = 1; rows <= 6; rows += 1) {
287       for (size_t channels = 1; channels <= 80; channels += 15) {
288         VMulCAddCMicrokernelTester()
289           .channel_tile(16)
290           .channels(channels)
291           .rows(rows)
292           .inplace(true)
293           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
294       }
295     }
296   }
297 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,qmin)298   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, qmin) {
299     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
300     for (size_t rows = 1; rows <= 6; rows += 1) {
301       for (size_t channels = 1; channels <= 80; channels += 15) {
302         VMulCAddCMicrokernelTester()
303           .channel_tile(16)
304           .channels(channels)
305           .rows(rows)
306           .qmin(128)
307           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
308       }
309     }
310   }
311 
TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X,qmax)312   TEST(F16_VMULCADDC_MINMAX_C16__NEONFP16ARITH_2X, qmax) {
313     TEST_REQUIRES_ARM_NEON_FP16_ARITH;
314     for (size_t rows = 1; rows <= 6; rows += 1) {
315       for (size_t channels = 1; channels <= 80; channels += 15) {
316         VMulCAddCMicrokernelTester()
317           .channel_tile(16)
318           .channels(channels)
319           .rows(rows)
320           .qmax(128)
321           .Test(xnn_f16_vmulcaddc_minmax_ukernel_c16__neonfp16arith_2x);
322       }
323     }
324   }
325 #endif  // XNN_ARCH_ARM64
326