1/*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <services/sdei_flags.h>
8
9#define LEVEL	0
10#define EDGE	2
11#define SDEI_NORMAL	0x70
12#define HIGHEST_SEC	0
13
14/memreserve/ 0x80000000 0x00010000;
15
16/ {
17};
18
19/ {
20	model = "FVP Base";
21	compatible = "arm,vfp-base", "arm,vexpress";
22	interrupt-parent = <&gic>;
23	#address-cells = <2>;
24	#size-cells = <2>;
25
26	chosen { };
27
28	aliases {
29		serial0 = &v2m_serial0;
30		serial1 = &v2m_serial1;
31		serial2 = &v2m_serial2;
32		serial3 = &v2m_serial3;
33	};
34
35	psci {
36		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
37		method = "smc";
38		cpu_suspend = <0xc4000001>;
39		cpu_off = <0x84000002>;
40		cpu_on = <0xc4000003>;
41		sys_poweroff = <0x84000008>;
42		sys_reset = <0x84000009>;
43		max-pwr-lvl = <2>;
44	};
45
46#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
47	firmware {
48#if SDEI_IN_FCONF
49		sdei {
50			compatible = "arm,sdei-1.0";
51			method = "smc";
52			private_event_count = <3>;
53			shared_event_count = <3>;
54			/*
55			 * Each event descriptor has typically 3 fields:
56			 * 1. Event number
57			 * 2. Interrupt number the event is bound to or
58			 *    if event is dynamic, specified as SDEI_DYN_IRQ
59			 * 3. Bit map of event flags
60			 */
61			private_events =	<1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
62						<1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
63						<1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
64			shared_events =		<2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
65						<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
66						<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
67		};
68#endif /* SDEI_IN_FCONF */
69
70#if SEC_INT_DESC_IN_FCONF
71		sec_interrupts {
72			compatible = "arm,secure_interrupt_desc";
73			/* Number of G0 and G1 secure interrupts defined by the platform */
74			g0_intr_cnt = <2>;
75			g1s_intr_cnt = <9>;
76			/*
77			 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
78			 * terminology. Each interrupt property descriptor has 3 fields:
79			 * 1. Interrupt number
80			 * 2. Interrupt priority
81			 * 3. Type of interrupt (Edge or Level configured)
82			 */
83			g0_intr_desc =	< 8 SDEI_NORMAL EDGE>,
84					<14 HIGHEST_SEC EDGE>;
85
86			g1s_intr_desc =	< 9 HIGHEST_SEC EDGE>,
87					<10 HIGHEST_SEC EDGE>,
88					<11 HIGHEST_SEC EDGE>,
89					<12 HIGHEST_SEC EDGE>,
90					<13 HIGHEST_SEC EDGE>,
91					<15 HIGHEST_SEC EDGE>,
92					<29 HIGHEST_SEC LEVEL>,
93					<56 HIGHEST_SEC LEVEL>,
94					<57 HIGHEST_SEC LEVEL>;
95		};
96#endif /* SEC_INT_DESC_IN_FCONF */
97	};
98#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */
99
100	cpus {
101		#address-cells = <2>;
102		#size-cells = <0>;
103
104		CPU_MAP
105
106		idle-states {
107			entry-method = "arm,psci";
108
109			CPU_SLEEP_0: cpu-sleep-0 {
110				compatible = "arm,idle-state";
111				local-timer-stop;
112				arm,psci-suspend-param = <0x0010000>;
113				entry-latency-us = <40>;
114				exit-latency-us = <100>;
115				min-residency-us = <150>;
116			};
117
118			CLUSTER_SLEEP_0: cluster-sleep-0 {
119				compatible = "arm,idle-state";
120				local-timer-stop;
121				arm,psci-suspend-param = <0x1010000>;
122				entry-latency-us = <500>;
123				exit-latency-us = <1000>;
124				min-residency-us = <2500>;
125			};
126		};
127
128		CPUS
129
130		L2_0: l2-cache0 {
131			compatible = "cache";
132		};
133	};
134
135	memory@80000000 {
136		device_type = "memory";
137		reg = <0x00000000 0x80000000 0 0x7F000000>,
138		      <0x00000008 0x80000000 0 0x80000000>;
139	};
140
141	gic: interrupt-controller@2f000000 {
142		compatible = "arm,gic-v3";
143		#interrupt-cells = <3>;
144		#address-cells = <2>;
145		#size-cells = <2>;
146		ranges;
147		interrupt-controller;
148		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
149		      <0x0 0x2f100000 0 0x200000>,	// GICR
150		      <0x0 0x2c000000 0 0x2000>,	// GICC
151		      <0x0 0x2c010000 0 0x2000>,	// GICH
152		      <0x0 0x2c02f000 0 0x2000>;	// GICV
153		interrupts = <1 9 4>;
154
155		its: its@2f020000 {
156			compatible = "arm,gic-v3-its";
157			msi-controller;
158			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
159		};
160	};
161
162	timer {
163		compatible = "arm,armv8-timer";
164		interrupts = <1 13 0xff01>,
165			     <1 14 0xff01>,
166			     <1 11 0xff01>,
167			     <1 10 0xff01>;
168		clock-frequency = <100000000>;
169	};
170
171	timer@2a810000 {
172			compatible = "arm,armv7-timer-mem";
173			reg = <0x0 0x2a810000 0x0 0x10000>;
174			clock-frequency = <100000000>;
175			#address-cells = <2>;
176			#size-cells = <2>;
177			ranges;
178			frame@2a830000 {
179				frame-number = <1>;
180				interrupts = <0 26 4>;
181				reg = <0x0 0x2a830000 0x0 0x10000>;
182			};
183	};
184
185	pmu {
186		compatible = "arm,armv8-pmuv3";
187		interrupts = <0 60 4>,
188			     <0 61 4>,
189			     <0 62 4>,
190			     <0 63 4>;
191	};
192
193	smb@0,0 {
194		compatible = "simple-bus";
195
196		#address-cells = <2>;
197		#size-cells = <1>;
198		ranges = <0 0 0 0x08000000 0x04000000>,
199			 <1 0 0 0x14000000 0x04000000>,
200			 <2 0 0 0x18000000 0x04000000>,
201			 <3 0 0 0x1c000000 0x04000000>,
202			 <4 0 0 0x0c000000 0x04000000>,
203			 <5 0 0 0x10000000 0x04000000>;
204
205		#include "rtsm_ve-motherboard.dtsi"
206	};
207
208	panels {
209		panel {
210			compatible	= "panel";
211			mode		= "XVGA";
212			refresh		= <60>;
213			xres		= <1024>;
214			yres		= <768>;
215			pixclock	= <15748>;
216			left_margin	= <152>;
217			right_margin	= <48>;
218			upper_margin	= <23>;
219			lower_margin	= <3>;
220			hsync_len	= <104>;
221			vsync_len	= <4>;
222			sync		= <0>;
223			vmode		= "FB_VMODE_NONINTERLACED";
224			tim2		= "TIM2_BCD", "TIM2_IPC";
225			cntl		= "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
226			caps		= "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
227			bpp		= <16>;
228		};
229	};
230};
231