1/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
9
10/ {
11
12	chosen {
13		stdout-path = "serial0:115200n8";
14	};
15
16	reserved-memory {
17		#address-cells = <2>;
18		#size-cells = <2>;
19		ranges;
20
21		secure-firmware@ff000000 {
22			reg = <0 0xff000000 0 0x01000000>;
23			no-map;
24		};
25	};
26
27	cpus {
28		#address-cells = <2>;
29		#size-cells = <0>;
30		cpu0@0 {
31			compatible = "arm,armv8";
32			reg = <0x0 0x0>;
33			device_type = "cpu";
34			enable-method = "psci";
35			clocks = <&scmi_dvfs 0>;
36		};
37		cpu1@100 {
38			compatible = "arm,armv8";
39			reg = <0x0 0x100>;
40			device_type = "cpu";
41			enable-method = "psci";
42			clocks = <&scmi_dvfs 0>;
43		};
44		cpu2@10000 {
45			compatible = "arm,armv8";
46			reg = <0x0 0x10000>;
47			device_type = "cpu";
48			enable-method = "psci";
49			clocks = <&scmi_dvfs 0>;
50		};
51		cpu3@10100 {
52			compatible = "arm,armv8";
53			reg = <0x0 0x10100>;
54			device_type = "cpu";
55			enable-method = "psci";
56			clocks = <&scmi_dvfs 0>;
57		};
58	};
59
60	/* The first bank of memory, memory map is actually provided by UEFI. */
61	memory@80000000 {
62		#address-cells = <2>;
63		#size-cells = <2>;
64		device_type = "memory";
65		/* [0x80000000-0xffffffff] */
66		reg = <0x00000000 0x80000000 0x0 0x80000000>;
67	};
68
69	memory@8080000000 {
70		#address-cells = <2>;
71		#size-cells = <2>;
72		device_type = "memory";
73		/* [0x8080000000-0x83ffffffff] */
74		reg = <0x00000080 0x80000000 0x1 0x80000000>;
75	};
76
77	virtio_block@1c170000 {
78		compatible = "virtio,mmio";
79		reg = <0x0 0x1c170000 0x0 0x200>;
80		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
81	};
82
83	virtio_net@1c180000 {
84		compatible = "virtio,mmio";
85		reg = <0x0 0x1c180000 0x0 0x200>;
86		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
87	};
88
89	virtio_rng@1c190000 {
90		compatible = "virtio,mmio";
91		reg = <0x0 0x1c190000 0x0 0x200>;
92		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
93	};
94
95	ethernet@1d100000 {
96		compatible = "smsc,lan91c111";
97		reg = <0x0 0x1d100000 0x0 0x10000>;
98		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
99	};
100
101	kmi@1c150000 {
102		compatible = "arm,pl050", "arm,primecell";
103		reg = <0x0 0x1c150000 0x0 0x1000>;
104		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
105		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
106		clock-names = "KMIREFCLK", "apb_pclk";
107	};
108
109	kmi@1c160000 {
110		compatible = "arm,pl050", "arm,primecell";
111		reg = <0x0 0x1c160000 0x0 0x1000>;
112		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
113		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
114		clock-names = "KMIREFCLK", "apb_pclk";
115	};
116
117	firmware {
118		scmi {
119			compatible = "arm,scmi";
120			mbox-names = "tx", "rx";
121			mboxes = <&mailbox 1 0 &mailbox 1 1>;
122			shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
123			#address-cells = <1>;
124			#size-cells = <0>;
125
126			scmi_dvfs: protocol@13 {
127				reg = <0x13>;
128				#clock-cells = <1>;
129			};
130		};
131	};
132
133	bp_clock24mhz: clock24mhz {
134		compatible = "fixed-clock";
135		#clock-cells = <0>;
136		clock-frequency = <24000000>;
137		clock-output-names = "bp:clock24mhz";
138	};
139};
140
141&gic {
142	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
143	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
144	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
145};
146