1/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier:     BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8#ifndef MARVELL_MACROS_S
9#define MARVELL_MACROS_S
10
11#include <drivers/arm/cci.h>
12#include <drivers/arm/gic_common.h>
13#include <drivers/arm/gicv2.h>
14#include <drivers/arm/gicv3.h>
15#include <platform_def.h>
16
17/*
18 *	These Macros are required by ATF
19 */
20
21.section .rodata.gic_reg_name, "aS"
22/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
23gicc_regs:
24	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
25
26#ifdef USE_CCI
27/* Applicable only to GICv3 with SRE enabled */
28icc_regs:
29	.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
30#endif
31/* Registers common to both GICv2 and GICv3 */
32gicd_pend_reg:
33	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
34		" Offset:\t\t\tvalue\n"
35newline:
36	.asciz "\n"
37spacer:
38	.asciz ":\t\t0x"
39
40	/* ---------------------------------------------
41	 * The below utility macro prints out relevant GIC
42	 * registers whenever an unhandled exception is
43	 * taken in BL31 on ARM standard platforms.
44	 * Expects: GICD base in x16, GICC base in x17
45	 * Clobbers: x0 - x10, sp
46	 * ---------------------------------------------
47	 */
48	.macro marvell_print_gic_regs
49	/* Check for GICv3 system register access */
50	mrs	x7, id_aa64pfr0_el1
51	ubfx	x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
52	cmp	x7, #1
53	b.ne	print_gicv2
54
55	/* Check for SRE enable */
56	mrs	x8, ICC_SRE_EL3
57	tst	x8, #ICC_SRE_SRE_BIT
58	b.eq	print_gicv2
59
60#ifdef USE_CCI
61	/* Load the icc reg list to x6 */
62	adr	x6, icc_regs
63	/* Load the icc regs to gp regs used by str_in_crash_buf_print */
64	mrs	x8, ICC_HPPIR0_EL1
65	mrs	x9, ICC_HPPIR1_EL1
66	mrs	x10, ICC_CTLR_EL3
67	/* Store to the crash buf and print to console */
68	bl	str_in_crash_buf_print
69#endif
70	b	print_gic_common
71
72print_gicv2:
73	/* Load the gicc reg list to x6 */
74	adr	x6, gicc_regs
75	/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
76	ldr	w8, [x17, #GICC_HPPIR]
77	ldr	w9, [x17, #GICC_AHPPIR]
78	ldr	w10, [x17, #GICC_CTLR]
79	/* Store to the crash buf and print to console */
80	bl	str_in_crash_buf_print
81
82print_gic_common:
83	/* Print the GICD_ISPENDR regs */
84	add	x7, x16, #GICD_ISPENDR
85	adr	x4, gicd_pend_reg
86	bl	asm_print_str
87gicd_ispendr_loop:
88	sub	x4, x7, x16
89	cmp	x4, #0x280
90	b.eq	exit_print_gic_regs
91	bl	asm_print_hex
92
93	adr	x4, spacer
94	bl	asm_print_str
95
96	ldr	x4, [x7], #8
97	bl	asm_print_hex
98
99	adr	x4, newline
100	bl	asm_print_str
101	b	gicd_ispendr_loop
102exit_print_gic_regs:
103	.endm
104
105
106.section .rodata.cci_reg_name, "aS"
107cci_iface_regs:
108	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
109
110	/* ------------------------------------------------
111	 * The below required platform porting macro prints
112	 * out relevant interconnect registers whenever an
113	 * unhandled exception is taken in BL31.
114	 * Clobbers: x0 - x9, sp
115	 * ------------------------------------------------
116	 */
117	.macro print_cci_regs
118#ifdef USE_CCI
119	adr	x6, cci_iface_regs
120	/* Store in x7 the base address of the first interface */
121	mov_imm	x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET(	\
122			PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX))
123	ldr	w8, [x7, #SNOOP_CTRL_REG]
124	/* Store in x7 the base address of the second interface */
125	mov_imm	x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET(	\
126			PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX))
127	ldr	w9, [x7, #SNOOP_CTRL_REG]
128	/* Store to the crash buf and print to console */
129	bl	str_in_crash_buf_print
130#endif
131	.endm
132
133
134#endif /* MARVELL_MACROS_S */
135