1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <common/debug.h>
9 #include <drivers/marvell/mci.h>
10 #include <drivers/marvell/mochi/ap_setup.h>
11 #include <drivers/marvell/mochi/cp110_setup.h>
12 #include <lib/mmio.h>
13
14 #include <armada_common.h>
15 #include <marvell_plat_priv.h>
16 #include <marvell_pm.h>
17 #include <mc_trustzone/mc_trustzone.h>
18 #include <plat_marvell.h>
19 #include <mss_ipc_drv.h>
20 #include <mss_mem.h>
21
22 /* In Armada-8k family AP806/AP807, CP0 connected to PIDI
23 * and CP1 connected to IHB via MCI #0
24 */
25 #define MVEBU_MCI0 0
26
27 static _Bool pm_fw_running;
28
29 /* Set a weak stub for platforms that don't need to configure GPIO */
30 #pragma weak marvell_gpio_config
marvell_gpio_config(void)31 int marvell_gpio_config(void)
32 {
33 return 0;
34 }
35
marvell_bl31_mpp_init(int cp)36 static void marvell_bl31_mpp_init(int cp)
37 {
38 uint32_t reg;
39
40 /* need to do for CP#0 only */
41 if (cp)
42 return;
43
44
45 /*
46 * Enable CP0 I2C MPPs (MPP: 37-38)
47 * U-Boot rely on proper MPP settings for I2C EEPROM usage
48 * (only for CP0)
49 */
50 reg = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4));
51 mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000);
52 }
53
marvell_bl31_mss_init(void)54 void marvell_bl31_mss_init(void)
55 {
56 struct mss_pm_ctrl_block *mss_pm_crtl =
57 (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE;
58
59 /* Check that the image was loaded successfully */
60 if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) {
61 NOTICE("MSS PM is not supported in this build\n");
62 return;
63 }
64
65 /* If we got here it means that the PM firmware is running */
66 pm_fw_running = 1;
67
68 INFO("MSS IPC init\n");
69
70 if (mss_pm_crtl->ipc_state == IPC_INITIALIZED)
71 mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE);
72 }
73
is_pm_fw_running(void)74 _Bool is_pm_fw_running(void)
75 {
76 return pm_fw_running;
77 }
78
79 /* For TrusTzone we treat the "target" field of addr_map_win
80 * struct as attribute
81 */
82 static const struct addr_map_win tz_map[] = {
83 {PLAT_MARVELL_ATF_BASE, 0x200000, TZ_PERM_ABORT}
84 };
85
86 /* Configure MC TrustZone regions */
marvell_bl31_security_setup(void)87 static void marvell_bl31_security_setup(void)
88 {
89 int tz_nr, win_id;
90
91 tz_nr = ARRAY_SIZE(tz_map);
92
93 for (win_id = 0; win_id < tz_nr; win_id++)
94 tz_enable_win(MVEBU_AP0, tz_map, win_id);
95 }
96
97 /* This function overruns the same function in marvell_bl31_setup.c */
bl31_plat_arch_setup(void)98 void bl31_plat_arch_setup(void)
99 {
100 int cp;
101 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
102
103 /* initialize the timer for mdelay/udelay functionality */
104 plat_delay_timer_init();
105
106 /* configure apn806 */
107 ap_init();
108
109 /* In marvell_bl31_plat_arch_setup, el3 mmu is configured.
110 * el3 mmu configuration MUST be called after apn806_init, if not,
111 * this will cause an hang in init_io_win
112 * (after setting the IO windows GCR values).
113 */
114 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
115 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
116 marvell_bl31_plat_arch_setup();
117
118 for (cp = 0; cp < CP_COUNT; cp++) {
119 cp110_init(MVEBU_CP_REGS_BASE(cp),
120 STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
121
122 marvell_bl31_mpp_init(cp);
123 }
124
125 for (cp = 1; cp < CP_COUNT; cp++)
126 mci_link_tune(cp - 1);
127
128 /* initialize IPC between MSS and ATF */
129 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
130 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
131 marvell_bl31_mss_init();
132
133 /* Configure GPIO */
134 marvell_gpio_config();
135
136 marvell_bl31_security_setup();
137 }
138