1 /*
2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <stdint.h>
8 
9 #include <arch_helpers.h>
10 #include <common/debug.h>
11 #include <lib/mmio.h>
12 #include <plat/common/platform.h>
13 
14 #include <mt_cpuxgpt.h>
15 
16 #define CPUXGPT_BASE	0x10200000
17 #define INDEX_BASE		(CPUXGPT_BASE+0x0674)
18 #define CTL_BASE		(CPUXGPT_BASE+0x0670)
19 
20 uint64_t normal_time_base;
21 uint64_t atf_time_base;
22 
sched_clock_init(uint64_t normal_base,uint64_t atf_base)23 void sched_clock_init(uint64_t normal_base, uint64_t atf_base)
24 {
25 	normal_time_base = normal_base;
26 	atf_time_base = atf_base;
27 }
28 
sched_clock(void)29 uint64_t sched_clock(void)
30 {
31 	uint64_t cval;
32 
33 	cval = (((read_cntpct_el0() - atf_time_base)*1000)/
34 		SYS_COUNTER_FREQ_IN_MHZ) + normal_time_base;
35 	return cval;
36 }
37 
38 /*
39   * Return: 0 - Trying to disable the CPUXGPT control bit,
40   * and not allowed to disable it.
41   * Return: 1 - reg_addr is not realted to disable the control bit.
42   */
check_cpuxgpt_write_permission(unsigned int reg_addr,unsigned int reg_value)43 unsigned char check_cpuxgpt_write_permission(unsigned int reg_addr,
44 	unsigned int reg_value)
45 {
46 	unsigned int idx;
47 	unsigned int ctl_val;
48 
49 	if (reg_addr == CTL_BASE) {
50 		idx = mmio_read_32(INDEX_BASE);
51 
52 		/* idx 0: CPUXGPT system control */
53 		if (idx == 0) {
54 			ctl_val = mmio_read_32(CTL_BASE);
55 			if (ctl_val & 1) {
56 				/*
57 				 * if enable bit already set,
58 				 * then bit 0 is not allow to set as 0
59 				 */
60 				if (!(reg_value & 1))
61 					return 0;
62 			}
63 		}
64 	}
65 	return 1;
66 }
67 
68