1 /*
2  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLATFORM_DEF_H
8 #define PLATFORM_DEF_H
9 
10 
11 #define PLAT_PRIMARY_CPU   0x0
12 
13 #define MT_GIC_BASE        0x0c000000
14 #define PLAT_MT_CCI_BASE   0x0c500000
15 #define MCUCFG_BASE        0x0c530000
16 
17 #define IO_PHYS            0x10000000
18 
19 /* Aggregate of all devices for MMU mapping */
20 #define MTK_DEV_RNG0_BASE    IO_PHYS
21 #define MTK_DEV_RNG0_SIZE    0x10000000
22 #define MTK_DEV_RNG1_BASE    (IO_PHYS + 0x10000000)
23 #define MTK_DEV_RNG1_SIZE    0x10000000
24 #define MTK_DEV_RNG2_BASE    0x0c000000
25 #define MTK_DEV_RNG2_SIZE    0x600000
26 #define MTK_MCDI_SRAM_BASE      0x11B000
27 #define MTK_MCDI_SRAM_MAP_SIZE  0x1000
28 
29 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
30 #define GPIO_BASE        (IO_PHYS + 0x00005000)
31 #define SPM_BASE         (IO_PHYS + 0x00006000)
32 #define PMIC_WRAP_BASE   (IO_PHYS + 0x00026000)
33 #define EMI_BASE         (IO_PHYS + 0x00219000)
34 #define EMI_MPU_BASE     (IO_PHYS + 0x00226000)
35 #define IOCFG_RM_BASE    (IO_PHYS + 0x01C20000)
36 #define IOCFG_BM_BASE    (IO_PHYS + 0x01D10000)
37 #define IOCFG_BL_BASE    (IO_PHYS + 0x01D30000)
38 #define IOCFG_BR_BASE    (IO_PHYS + 0x01D40000)
39 #define IOCFG_LM_BASE    (IO_PHYS + 0x01E20000)
40 #define IOCFG_LB_BASE    (IO_PHYS + 0x01E70000)
41 #define IOCFG_RT_BASE    (IO_PHYS + 0x01EA0000)
42 #define IOCFG_LT_BASE    (IO_PHYS + 0x01F20000)
43 #define IOCFG_TL_BASE    (IO_PHYS + 0x01F30000)
44 /*******************************************************************************
45  * UART related constants
46  ******************************************************************************/
47 #define UART0_BASE    (IO_PHYS + 0x01002000)
48 #define UART1_BASE    (IO_PHYS + 0x01003000)
49 
50 #define UART_BAUDRATE 115200
51 
52 /*******************************************************************************
53  * System counter frequency related constants
54  ******************************************************************************/
55 #define SYS_COUNTER_FREQ_IN_TICKS    13000000
56 #define SYS_COUNTER_FREQ_IN_MHZ      13
57 
58 /*******************************************************************************
59  * GIC-400 & interrupt handling related constants
60  ******************************************************************************/
61 
62 /* Base MTK_platform compatible GIC memory map */
63 #define BASE_GICD_BASE        MT_GIC_BASE
64 #define MT_GIC_RDIST_BASE     (MT_GIC_BASE + 0x40000)
65 
66 /*******************************************************************************
67  * Platform binary types for linking
68  ******************************************************************************/
69 #define PLATFORM_LINKER_FORMAT      "elf64-littleaarch64"
70 #define PLATFORM_LINKER_ARCH        aarch64
71 
72 /*******************************************************************************
73  * Generic platform constants
74  ******************************************************************************/
75 #define PLATFORM_STACK_SIZE    0x800
76 
77 #define PLAT_MAX_PWR_LVL        U(3)
78 #define PLAT_MAX_RET_STATE      U(1)
79 #define PLAT_MAX_OFF_STATE      U(9)
80 
81 #define PLATFORM_SYSTEM_COUNT           U(1)
82 #define PLATFORM_MCUSYS_COUNT           U(1)
83 #define PLATFORM_CLUSTER_COUNT          U(1)
84 #define PLATFORM_CLUSTER0_CORE_COUNT    U(8)
85 #define PLATFORM_CORE_COUNT             (PLATFORM_CLUSTER0_CORE_COUNT)
86 #define PLATFORM_MAX_CPUS_PER_CLUSTER   U(8)
87 
88 #define SOC_CHIP_ID			U(0x8192)
89 
90 /*******************************************************************************
91  * Platform memory map related constants
92  ******************************************************************************/
93 #define TZRAM_BASE          0x54600000
94 #define TZRAM_SIZE          0x00030000
95 
96 /*******************************************************************************
97  * BL31 specific defines.
98  ******************************************************************************/
99 /*
100  * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
101  * present). BL31_BASE is calculated using the current BL31 debug size plus a
102  * little space for growth.
103  */
104 #define BL31_BASE       (TZRAM_BASE + 0x1000)
105 #define BL31_LIMIT      (TZRAM_BASE + TZRAM_SIZE)
106 
107 /*******************************************************************************
108  * Platform specific page table and MMU setup constants
109  ******************************************************************************/
110 #define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
111 #define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
112 #define MAX_XLAT_TABLES             16
113 #define MAX_MMAP_REGIONS            16
114 
115 /*******************************************************************************
116  * Declarations and constants to access the mailboxes safely. Each mailbox is
117  * aligned on the biggest cache line size in the platform. This is known only
118  * to the platform as it might have a combination of integrated and external
119  * caches. Such alignment ensures that two maiboxes do not sit on the same cache
120  * line at any cache level. They could belong to different cpus/clusters &
121  * get written while being protected by different locks causing corruption of
122  * a valid mailbox address.
123  ******************************************************************************/
124 #define CACHE_WRITEBACK_SHIFT    6
125 #define CACHE_WRITEBACK_GRANULE  (1 << CACHE_WRITEBACK_SHIFT)
126 #endif /* PLATFORM_DEF_H */
127