1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9
10 #include <platform_def.h>
11
12 #include <arch.h>
13 #include <arch_helpers.h>
14 #include <common/debug.h>
15 #include <drivers/delay_timer.h>
16 #include <denver.h>
17 #include <lib/mmio.h>
18 #include <lib/psci/psci.h>
19
20 #include <flowctrl.h>
21 #include <pmc.h>
22 #include <tegra_def.h>
23 #include <tegra_private.h>
24
25 /*
26 * Register used to clear CPU reset signals. Each CPU has two reset
27 * signals: CPU reset (3:0) and Core reset (19:16)
28 */
29 #define CPU_CMPLX_RESET_CLR 0x344
30 #define CPU_CORE_RESET_MASK 0x10001
31
32 /* Clock and Reset controller registers for system clock's settings */
33 #define SCLK_RATE 0x30
34 #define SCLK_BURST_POLICY 0x28
35 #define SCLK_BURST_POLICY_DEFAULT 0x10000000
36
37 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
38
tegra_soc_get_target_pwr_state(uint32_t lvl,const plat_local_state_t * states,uint32_t ncpu)39 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
40 const plat_local_state_t *states,
41 uint32_t ncpu)
42 {
43 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
44 uint32_t num_cpu = ncpu;
45 const plat_local_state_t *local_state = states;
46
47 (void)lvl;
48
49 assert(ncpu != 0U);
50
51 do {
52 temp = *local_state;
53 if ((temp < target)) {
54 target = temp;
55 }
56 --num_cpu;
57 local_state++;
58 } while (num_cpu != 0U);
59
60 return target;
61 }
62
tegra_soc_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)63 int32_t tegra_soc_validate_power_state(unsigned int power_state,
64 psci_power_state_t *req_state)
65 {
66 int state_id = psci_get_pstate_id(power_state);
67 int cpu = read_mpidr() & MPIDR_CPU_MASK;
68
69 /*
70 * Sanity check the requested state id, power level and CPU number.
71 * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
72 * i.e. CPU 0
73 */
74 if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) {
75 ERROR("unsupported state id @ power level\n");
76 return PSCI_E_INVALID_PARAMS;
77 }
78
79 /* Set lower power states to PLAT_MAX_OFF_STATE */
80 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
81 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
82
83 /* Set the SYSTEM_SUSPEND state-id */
84 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
85 PSTATE_ID_SOC_POWERDN;
86
87 return PSCI_E_SUCCESS;
88 }
89
tegra_soc_pwr_domain_on(u_register_t mpidr)90 int tegra_soc_pwr_domain_on(u_register_t mpidr)
91 {
92 int cpu = mpidr & MPIDR_CPU_MASK;
93 uint32_t mask = CPU_CORE_RESET_MASK << cpu;
94
95 if (cpu_powergate_mask[cpu] == 0) {
96
97 /* Deassert CPU reset signals */
98 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
99
100 /* Power on CPU using PMC */
101 tegra_pmc_cpu_on(cpu);
102
103 /* Fill in the CPU powergate mask */
104 cpu_powergate_mask[cpu] = 1;
105
106 } else {
107 /* Power on CPU using Flow Controller */
108 tegra_fc_cpu_on(cpu);
109 }
110
111 return PSCI_E_SUCCESS;
112 }
113
tegra_soc_pwr_domain_on_finish(const psci_power_state_t * target_state)114 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
115 {
116 /*
117 * Lock scratch registers which hold the CPU vectors
118 */
119 tegra_pmc_lock_cpu_vectors();
120
121 return PSCI_E_SUCCESS;
122 }
123
tegra_soc_pwr_domain_off(const psci_power_state_t * target_state)124 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
125 {
126 uint64_t val;
127
128 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
129
130 /* Disable DCO operations */
131 denver_disable_dco();
132
133 /* Power down the CPU */
134 val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
135 write_actlr_el1(val | DENVER_CPU_STATE_POWER_DOWN);
136
137 return PSCI_E_SUCCESS;
138 }
139
tegra_soc_cpu_standby(plat_local_state_t cpu_state)140 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
141 {
142 (void)cpu_state;
143 return PSCI_E_SUCCESS;
144 }
145
tegra_soc_pwr_domain_suspend(const psci_power_state_t * target_state)146 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
147 {
148 uint64_t val;
149
150 #if ENABLE_ASSERTIONS
151 int cpu = read_mpidr() & MPIDR_CPU_MASK;
152
153 /* SYSTEM_SUSPEND only on CPU0 */
154 assert(cpu == 0);
155 #endif
156
157 /* Allow restarting CPU #1 using PMC on suspend exit */
158 cpu_powergate_mask[1] = 0;
159
160 /* Program FC to enter suspend state */
161 tegra_fc_cpu_powerdn(read_mpidr());
162
163 /* Disable DCO operations */
164 denver_disable_dco();
165
166 /* Program the suspend state ID */
167 val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
168 write_actlr_el1(val | target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
169
170 return PSCI_E_SUCCESS;
171 }
172
tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t * target_state)173 int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
174 {
175 return PSCI_E_NOT_SUPPORTED;
176 }
177
tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t * target_state)178 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
179 {
180 return PSCI_E_SUCCESS;
181 }
182
tegra_soc_prepare_system_reset(void)183 int tegra_soc_prepare_system_reset(void)
184 {
185 /*
186 * Set System Clock (SCLK) to POR default so that the clock source
187 * for the PMC APB clock would not be changed due to system reset.
188 */
189 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
190 SCLK_BURST_POLICY_DEFAULT);
191 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
192
193 /* Wait 1 ms to make sure clock source/device logic is stabilized. */
194 mdelay(1);
195
196 /*
197 * Program the PMC in order to restart the system.
198 */
199 tegra_pmc_system_reset();
200
201 return PSCI_E_SUCCESS;
202 }
203
tegra_soc_prepare_system_off(void)204 __dead2 void tegra_soc_prepare_system_off(void)
205 {
206 ERROR("Tegra System Off: operation not handled.\n");
207 panic();
208 }
209