1 /*
2  * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MCE_PRIVATE_H
8 #define MCE_PRIVATE_H
9 
10 #include <stdbool.h>
11 #include <tegra_def.h>
12 
13 /*******************************************************************************
14  * Macros to prepare CSTATE info request
15  ******************************************************************************/
16 /* Description of the parameters for UPDATE_CSTATE_INFO request */
17 #define CLUSTER_CSTATE_MASK			0x7U
18 #define CLUSTER_CSTATE_SHIFT			0X0U
19 #define CLUSTER_CSTATE_UPDATE_BIT		(1U << 7)
20 #define CCPLEX_CSTATE_MASK			0x7U
21 #define CCPLEX_CSTATE_SHIFT			8U
22 #define CCPLEX_CSTATE_UPDATE_BIT		(1U << 15)
23 #define SYSTEM_CSTATE_MASK			0xFU
24 #define SYSTEM_CSTATE_SHIFT			16U
25 #define SYSTEM_CSTATE_UPDATE_BIT		(1U << 23)
26 #define CSTATE_WAKE_MASK_UPDATE_BIT		(1U << 31)
27 #define CSTATE_WAKE_MASK_SHIFT			32U
28 #define CSTATE_WAKE_MASK_CLEAR			0xFFFFFFFFU
29 
30 /*******************************************************************************
31  * Core ID mask (bits 3:0 in the online request)
32  ******************************************************************************/
33 #define MCE_CORE_ID_MASK			0xFU
34 
35 /*******************************************************************************
36  * C-state statistics macros
37  ******************************************************************************/
38 #define MCE_STAT_ID_SHIFT			16U
39 
40 /*******************************************************************************
41  * Security config macros
42  ******************************************************************************/
43 #define STRICT_CHECKING_ENABLED_SET		(1UL << 0)
44 #define STRICT_CHECKING_LOCKED_SET		(1UL << 1)
45 
46 /* declarations for NVG handler functions */
47 uint64_t nvg_get_version(void);
48 void nvg_set_wake_time(uint32_t wake_time);
49 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
50 		uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
51 int32_t nvg_set_cstate_stat_query_value(uint64_t data);
52 uint64_t nvg_get_cstate_stat_query_value(void);
53 int32_t nvg_is_sc7_allowed(void);
54 int32_t nvg_online_core(uint32_t core);
55 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
56 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
57 int32_t nvg_roc_clean_cache_trbits(void);
58 void nvg_enable_strict_checking_mode(void);
59 void nvg_verify_strict_checking_mode(void);
60 void nvg_system_shutdown(void);
61 void nvg_system_reboot(void);
62 void nvg_clear_hsm_corr_status(void);
63 
64 /* declarations for assembly functions */
65 void nvg_set_request_data(uint64_t req, uint64_t data);
66 void nvg_set_request(uint64_t req);
67 uint64_t nvg_get_result(void);
68 uint64_t nvg_cache_clean(void);
69 uint64_t nvg_cache_clean_inval(void);
70 uint64_t nvg_cache_inval_all(void);
71 
72 /* MCE helper functions */
73 void mce_enable_strict_checking(void);
74 void mce_verify_strict_checking(void);
75 void mce_system_shutdown(void);
76 void mce_system_reboot(void);
77 void mce_clear_hsm_corr_status(void);
78 
79 #endif /* MCE_PRIVATE_H */
80