1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <bl32_param.h> 15 #include <rk3288_def.h> 16 17 /******************************************************************************* 18 * Platform binary types for linking 19 ******************************************************************************/ 20 #define PLATFORM_LINKER_FORMAT "elf32-littlearm" 21 #define PLATFORM_LINKER_ARCH arm 22 23 /******************************************************************************* 24 * Generic platform constants 25 ******************************************************************************/ 26 27 /* Size of cacheable stacks */ 28 #if defined(IMAGE_BL1) 29 #define PLATFORM_STACK_SIZE 0x440 30 #elif defined(IMAGE_BL2) 31 #define PLATFORM_STACK_SIZE 0x400 32 #elif defined(IMAGE_BL32) 33 #define PLATFORM_STACK_SIZE 0x800 34 #endif 35 36 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 37 38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 39 #define PLATFORM_SYSTEM_COUNT U(1) 40 #define PLATFORM_CLUSTER_COUNT U(1) 41 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 42 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 43 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 44 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 45 PLATFORM_CLUSTER_COUNT + \ 46 PLATFORM_CORE_COUNT) 47 48 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 49 50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 51 52 /* 53 * This macro defines the deepest retention state possible. A higher state 54 * id will represent an invalid or a power down state. 55 */ 56 #define PLAT_MAX_RET_STATE U(1) 57 58 /* 59 * This macro defines the deepest power down states possible. Any state ID 60 * higher than this is invalid. 61 */ 62 #define PLAT_MAX_OFF_STATE U(2) 63 64 /******************************************************************************* 65 * Platform specific page table and MMU setup constants 66 ******************************************************************************/ 67 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 68 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 69 #define MAX_XLAT_TABLES 8 70 #define MAX_MMAP_REGIONS 18 71 72 /******************************************************************************* 73 * Declarations and constants to access the mailboxes safely. Each mailbox is 74 * aligned on the biggest cache line size in the platform. This is known only 75 * to the platform as it might have a combination of integrated and external 76 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 77 * line at any cache level. They could belong to different cpus/clusters & 78 * get written while being protected by different locks causing corruption of 79 * a valid mailbox address. 80 ******************************************************************************/ 81 #define CACHE_WRITEBACK_SHIFT 6 82 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 83 84 /* 85 * Define GICD and GICC and GICR base 86 */ 87 #define PLAT_RK_GICD_BASE RK3288_GICD_BASE 88 #define PLAT_RK_GICC_BASE RK3288_GICC_BASE 89 90 #define PLAT_RK_UART_BASE UART2_BASE 91 #define PLAT_RK_UART_CLOCK RK3288_UART_CLOCK 92 #define PLAT_RK_UART_BAUDRATE RK3288_BAUDRATE 93 94 /* ClusterId is always 0x5 on rk3288, filter it */ 95 #define PLAT_RK_MPIDR_CLUSTER_MASK 0 96 #define PLAT_RK_PRIMARY_CPU 0x0 97 98 #define PSRAM_DO_DDR_RESUME 0 99 #define PSRAM_CHECK_WAKEUP_CPU 0 100 101 #endif /* PLATFORM_DEF_H */ 102