1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <bl31_param.h> 15 #include <rk3399_def.h> 16 17 /******************************************************************************* 18 * Platform binary types for linking 19 ******************************************************************************/ 20 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 21 #define PLATFORM_LINKER_ARCH aarch64 22 23 /******************************************************************************* 24 * Generic platform constants 25 ******************************************************************************/ 26 27 /* Size of cacheable stacks */ 28 #if defined(IMAGE_BL1) 29 #define PLATFORM_STACK_SIZE 0x440 30 #elif defined(IMAGE_BL2) 31 #define PLATFORM_STACK_SIZE 0x400 32 #elif defined(IMAGE_BL31) 33 #define PLATFORM_STACK_SIZE 0x800 34 #elif defined(IMAGE_BL32) 35 #define PLATFORM_STACK_SIZE 0x440 36 #endif 37 38 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 39 40 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 41 #define PLATFORM_SYSTEM_COUNT U(1) 42 #define PLATFORM_CLUSTER_COUNT U(2) 43 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 44 #define PLATFORM_CLUSTER1_CORE_COUNT U(2) 45 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 46 PLATFORM_CLUSTER0_CORE_COUNT) 47 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 48 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 49 PLATFORM_CLUSTER_COUNT + \ 50 PLATFORM_CORE_COUNT) 51 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 52 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 53 54 /* 55 * This macro defines the deepest retention state possible. A higher state 56 * id will represent an invalid or a power down state. 57 */ 58 #define PLAT_MAX_RET_STATE U(1) 59 60 /* 61 * This macro defines the deepest power down states possible. Any state ID 62 * higher than this is invalid. 63 */ 64 #define PLAT_MAX_OFF_STATE U(2) 65 66 /******************************************************************************* 67 * Platform specific page table and MMU setup constants 68 ******************************************************************************/ 69 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 70 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 71 #define MAX_XLAT_TABLES 20 72 #define MAX_MMAP_REGIONS 25 73 74 /******************************************************************************* 75 * Declarations and constants to access the mailboxes safely. Each mailbox is 76 * aligned on the biggest cache line size in the platform. This is known only 77 * to the platform as it might have a combination of integrated and external 78 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 79 * line at any cache level. They could belong to different cpus/clusters & 80 * get written while being protected by different locks causing corruption of 81 * a valid mailbox address. 82 ******************************************************************************/ 83 #define CACHE_WRITEBACK_SHIFT 6 84 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 85 86 /* 87 * Define GICD and GICC and GICR base 88 */ 89 #define PLAT_RK_GICD_BASE BASE_GICD_BASE 90 #define PLAT_RK_GICR_BASE BASE_GICR_BASE 91 #define PLAT_RK_GICC_BASE 0 92 93 #define PLAT_RK_UART_BASE UART2_BASE 94 #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK 95 #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE 96 97 #define PLAT_RK_CCI_BASE CCI500_BASE 98 99 #define PLAT_RK_PRIMARY_CPU 0x0 100 101 #define PSRAM_DO_DDR_RESUME 1 102 #define PSRAM_CHECK_WAKEUP_CPU 0 103 104 #endif /* PLATFORM_DEF_H */ 105