1#!/usr/bin/env python
2
3# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
4
5from __future__ import print_function
6from capstone import *
7from capstone.arm64 import *
8from xprint import to_hex, to_x
9
10
11ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
12
13all_tests = (
14        (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
15        )
16
17
18def print_insn_detail(insn):
19    # print address, mnemonic and operands
20    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
21
22    # "data" instruction generated by SKIPDATA option has no detail
23    if insn.id == 0:
24        return
25
26    if len(insn.operands) > 0:
27        print("\top_count: %u" % len(insn.operands))
28        c = -1
29        for i in insn.operands:
30            c += 1
31            if i.type == ARM64_OP_REG:
32                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
33            if i.type == ARM64_OP_IMM:
34                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
35            if i.type == ARM64_OP_CIMM:
36                print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
37            if i.type == ARM64_OP_FP:
38                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
39            if i.type == ARM64_OP_MEM:
40                print("\t\toperands[%u].type: MEM" % c)
41                if i.mem.base != 0:
42                    print("\t\t\toperands[%u].mem.base: REG = %s" \
43                        % (c, insn.reg_name(i.mem.base)))
44                if i.mem.index != 0:
45                    print("\t\t\toperands[%u].mem.index: REG = %s" \
46                        % (c, insn.reg_name(i.mem.index)))
47                if i.mem.disp != 0:
48                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
49                        % (c, to_x(i.mem.disp)))
50            if i.type == ARM64_OP_REG_MRS:
51                print("\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg))
52            if i.type == ARM64_OP_REG_MSR:
53                print("\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg))
54            if i.type == ARM64_OP_PSTATE:
55                print("\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate))
56            if i.type == ARM64_OP_SYS:
57                print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys))
58            if i.type == ARM64_OP_PREFETCH:
59                print("\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch))
60            if i.type == ARM64_OP_BARRIER:
61                print("\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier))
62
63            if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
64                print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
65
66            if i.ext != ARM64_EXT_INVALID:
67                print("\t\t\tExt: %u" % i.ext)
68
69            if i.vas != ARM64_VAS_INVALID:
70                print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
71
72            if i.vess != ARM64_VESS_INVALID:
73                print("\t\t\tVector Element Size Specifier: %u" % i.vess)
74
75            if i.vector_index != -1:
76                print("\t\t\tVector Index: %u" % i.vector_index)
77
78            if i.access == CS_AC_READ:
79                print("\t\toperands[%u].access: READ\n" % (c))
80            elif i.access == CS_AC_WRITE:
81                print("\t\toperands[%u].access: WRITE\n" % (c))
82            elif i.access == CS_AC_READ | CS_AC_WRITE:
83                print("\t\toperands[%u].access: READ | WRITE\n" % (c))
84
85
86    if insn.writeback:
87        print("\tWrite-back: True")
88    if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
89        print("\tCode-condition: %u" % insn.cc)
90    if insn.update_flags:
91        print("\tUpdate-flags: True")
92
93    (regs_read, regs_write) = insn.regs_access()
94
95    if len(regs_read) > 0:
96        print("\tRegisters read:", end="")
97        for r in regs_read:
98            print(" %s" %(insn.reg_name(r)), end="")
99        print("")
100
101    if len(regs_write) > 0:
102        print("\tRegisters modified:", end="")
103        for r in regs_write:
104            print(" %s" %(insn.reg_name(r)), end="")
105        print("")
106
107
108# ## Test class Cs
109def test_class():
110
111    for (arch, mode, code, comment) in all_tests:
112        print("*" * 16)
113        print("Platform: %s" % comment)
114        print("Code: %s" % to_hex(code))
115        print("Disasm:")
116
117        try:
118            md = Cs(arch, mode)
119            md.detail = True
120            for insn in md.disasm(code, 0x2c):
121                print_insn_detail(insn)
122                print ()
123            print("0x%x:\n" % (insn.address + insn.size))
124        except CsError as e:
125            print("ERROR: %s" % e)
126
127
128if __name__ == '__main__':
129    test_class()
130