1 /* Capstone testing regression */
2 /* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
3
4
5 #include "factory.h"
6
get_detail_arm64(csh * handle,cs_mode mode,cs_insn * ins)7 char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
8 {
9 cs_arm64 *arm64;
10 int i;
11 cs_regs regs_read, regs_write;
12 uint8_t regs_read_count, regs_write_count;
13 uint8_t access;
14 char *result;
15
16 result = (char *)malloc(sizeof(char));
17 result[0] = '\0';
18
19 // detail can be NULL if SKIPDATA option is turned ON
20 if (ins->detail == NULL)
21 return result;
22
23 arm64 = &(ins->detail->arm64);
24 if (arm64->op_count)
25 add_str(&result, " ; op_count: %u", arm64->op_count);
26
27 for (i = 0; i < arm64->op_count; i++) {
28 cs_arm64_op *op = &(arm64->operands[i]);
29 switch(op->type) {
30 default:
31 break;
32 case ARM64_OP_REG:
33 add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
34 break;
35 case ARM64_OP_IMM:
36 add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
37 break;
38 case ARM64_OP_FP:
39 #if defined(_KERNEL_MODE)
40 // Issue #681: Windows kernel does not support formatting float point
41 add_str(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
42 #else
43 add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp);
44 #endif
45 break;
46 case ARM64_OP_MEM:
47 add_str(&result, " ; operands[%u].type: MEM", i);
48 if (op->mem.base != ARM64_REG_INVALID)
49 add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
50 if (op->mem.index != ARM64_REG_INVALID)
51 add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
52 if (op->mem.disp != 0)
53 add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
54
55 break;
56 case ARM64_OP_CIMM:
57 add_str(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm);
58 break;
59 case ARM64_OP_REG_MRS:
60 add_str(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg);
61 break;
62 case ARM64_OP_REG_MSR:
63 add_str(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg);
64 break;
65 case ARM64_OP_PSTATE:
66 add_str(&result, " ; operands[%u].type: PSTATE = 0x%x", i, op->pstate);
67 break;
68 case ARM64_OP_SYS:
69 add_str(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys);
70 break;
71 case ARM64_OP_PREFETCH:
72 add_str(&result, " ; operands[%u].type: PREFETCH = 0x%x", i, op->prefetch);
73 break;
74 case ARM64_OP_BARRIER:
75 add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier);
76 break;
77 }
78
79 access = op->access;
80 switch(access) {
81 default:
82 break;
83 case CS_AC_READ:
84 add_str(&result, " ; operands[%u].access: READ", i);
85 break;
86 case CS_AC_WRITE:
87 add_str(&result, " ; operands[%u].access: WRITE", i);
88 break;
89 case CS_AC_READ | CS_AC_WRITE:
90 add_str(&result, " ; operands[%u].access: READ | WRITE", i);
91 break;
92 }
93
94 if (op->shift.type != ARM64_SFT_INVALID && op->shift.value)
95 add_str(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value);
96
97 if (op->ext != ARM64_EXT_INVALID)
98 add_str(&result, " ; Ext: %u", op->ext);
99
100 if (op->vas != ARM64_VAS_INVALID)
101 add_str(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas);
102
103 if (op->vess != ARM64_VESS_INVALID)
104 add_str(&result, " ; Vector Element Size Specifier: %u", op->vess);
105
106 if (op->vector_index != -1)
107 add_str(&result, " ; Vector Index: %u", op->vector_index);
108 }
109
110 if (arm64->update_flags)
111 add_str(&result, " ; Update-flags: True");
112
113 if (arm64->writeback)
114 add_str(&result, " ; Write-back: True");
115
116 if (arm64->cc)
117 add_str(&result, " ; Code-condition: %u", arm64->cc);
118
119 if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) {
120 if (regs_read_count) {
121 add_str(&result, " ; Registers read:");
122 for(i = 0; i < regs_read_count; i++) {
123 add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
124 }
125 }
126
127 if (regs_write_count) {
128 add_str(&result, " ; Registers modified:");
129 for(i = 0; i < regs_write_count; i++) {
130 add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));
131 }
132 }
133 }
134
135 return result;
136 }
137