1 #include <stdint.h>
2
3 #include <cpuinfo.h>
4 #include <x86/api.h>
5
6
cpuinfo_x86_decode_cache_descriptor(uint8_t descriptor,enum cpuinfo_vendor vendor,const struct cpuinfo_x86_model_info * model_info,struct cpuinfo_x86_caches * cache,struct cpuinfo_tlb * itlb_4KB,struct cpuinfo_tlb * itlb_2MB,struct cpuinfo_tlb * itlb_4MB,struct cpuinfo_tlb * dtlb0_4KB,struct cpuinfo_tlb * dtlb0_2MB,struct cpuinfo_tlb * dtlb0_4MB,struct cpuinfo_tlb * dtlb_4KB,struct cpuinfo_tlb * dtlb_2MB,struct cpuinfo_tlb * dtlb_4MB,struct cpuinfo_tlb * dtlb_1GB,struct cpuinfo_tlb * stlb2_4KB,struct cpuinfo_tlb * stlb2_2MB,struct cpuinfo_tlb * stlb2_1GB,uint32_t * prefetch_size)7 void cpuinfo_x86_decode_cache_descriptor(
8 uint8_t descriptor, enum cpuinfo_vendor vendor,
9 const struct cpuinfo_x86_model_info* model_info,
10 struct cpuinfo_x86_caches* cache,
11 struct cpuinfo_tlb* itlb_4KB,
12 struct cpuinfo_tlb* itlb_2MB,
13 struct cpuinfo_tlb* itlb_4MB,
14 struct cpuinfo_tlb* dtlb0_4KB,
15 struct cpuinfo_tlb* dtlb0_2MB,
16 struct cpuinfo_tlb* dtlb0_4MB,
17 struct cpuinfo_tlb* dtlb_4KB,
18 struct cpuinfo_tlb* dtlb_2MB,
19 struct cpuinfo_tlb* dtlb_4MB,
20 struct cpuinfo_tlb* dtlb_1GB,
21 struct cpuinfo_tlb* stlb2_4KB,
22 struct cpuinfo_tlb* stlb2_2MB,
23 struct cpuinfo_tlb* stlb2_1GB,
24 uint32_t* prefetch_size)
25 {
26 /*
27 * Descriptors are parsed according to:
28 * - Application Note 485: Intel Processor Indentification and CPUID Instruction, May 2012, Order Number 241618-039
29 * - Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2 (2A, 2B, 2C & 2D): Instruction Set
30 * Reference, A-Z, December 2016. Order Number: 325383-061US
31 * - Cyrix CPU Detection Guide, Preliminary Revision 1.01
32 * - Geode(TM) GX1 Processor Series: Low Power Integrated x86 Solution
33 */
34 switch (descriptor) {
35 case 0x01:
36 /*
37 * Intel ISA Reference:
38 * "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries"
39 * Application Note 485:
40 * "Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries"
41 */
42 *itlb_4KB = (struct cpuinfo_tlb) {
43 .entries = 32,
44 .associativity = 4,
45 .pages = CPUINFO_PAGE_SIZE_4KB,
46 };
47 break;
48 case 0x02:
49 /*
50 * Intel ISA Reference:
51 * "Instruction TLB: 4 MByte pages, fully associative, 2 entries"
52 * Application Note 485:
53 * "Instruction TLB: 4-MB Pages, fully associative, 2 entries"
54 */
55 *itlb_4MB = (struct cpuinfo_tlb) {
56 .entries = 2,
57 .associativity = 2,
58 .pages = CPUINFO_PAGE_SIZE_4MB,
59 };
60 break;
61 case 0x03:
62 /*
63 * Intel ISA Reference:
64 * "Data TLB: 4 KByte pages, 4-way set associative, 64 entries"
65 * Application Note 485:
66 * "Data TLB: 4-KB Pages, 4-way set associative, 64 entries"
67 */
68 *dtlb_4KB = (struct cpuinfo_tlb) {
69 .entries = 64,
70 .associativity = 4,
71 .pages = CPUINFO_PAGE_SIZE_4KB,
72 };
73 break;
74 case 0x04:
75 /*
76 * Intel ISA Reference:
77 * "Data TLB: 4 MByte pages, 4-way set associative, 8 entries"
78 * Application Note 485:
79 * "Data TLB: 4-MB Pages, 4-way set associative, 8 entries"
80 */
81 *dtlb_4MB = (struct cpuinfo_tlb) {
82 .entries = 8,
83 .associativity = 4,
84 .pages = CPUINFO_PAGE_SIZE_4MB,
85 };
86 break;
87 case 0x05:
88 /*
89 * Intel ISA Reference:
90 * "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries"
91 * Application Note 485:
92 * "Data TLB: 4-MB Pages, 4-way set associative, 32 entries"
93 */
94 *dtlb_4MB = (struct cpuinfo_tlb) {
95 .entries = 32,
96 .associativity = 4,
97 .pages = CPUINFO_PAGE_SIZE_4MB,
98 };
99 break;
100 case 0x06:
101 /*
102 * Intel ISA Reference:
103 * "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size"
104 * Application Note 485:
105 * "1st-level instruction cache: 8-KB, 4-way set associative, 32-byte line size"
106 */
107 cache->l1i = (struct cpuinfo_x86_cache) {
108 .size = 8 * 1024,
109 .associativity = 4,
110 .sets = 64,
111 .partitions = 1,
112 .line_size = 32,
113 };
114 break;
115 case 0x08:
116 /*
117 * Intel ISA Reference:
118 * "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size"
119 * Application Note 485:
120 * "1st-level instruction cache: 16-KB, 4-way set associative, 32-byte line size"
121 */
122 cache->l1i = (struct cpuinfo_x86_cache) {
123 .size = 16 * 1024,
124 .associativity = 4,
125 .sets = 128,
126 .partitions = 1,
127 .line_size = 32,
128 };
129 break;
130 case 0x09:
131 /*
132 * Intel ISA Reference:
133 * "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size"
134 * Application Note 485:
135 * "1st-level Instruction Cache: 32-KB, 4-way set associative, 64-byte line size"
136 */
137 cache->l1i = (struct cpuinfo_x86_cache) {
138 .size = 32 * 1024,
139 .associativity = 4,
140 .sets = 128,
141 .partitions = 1,
142 .line_size = 64,
143 };
144 break;
145 case 0x0A:
146 /*
147 * Intel ISA Reference:
148 * "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size"
149 * Application Note 485:
150 * "1st-level data cache: 8-KB, 2-way set associative, 32-byte line size"
151 */
152 cache->l1d = (struct cpuinfo_x86_cache) {
153 .size = 8 * 1024,
154 .associativity = 2,
155 .sets = 128,
156 .partitions = 1,
157 .line_size = 32,
158 };
159 break;
160 case 0x0B:
161 /*
162 * Intel ISA Reference:
163 * "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries"
164 * Application Note 485:
165 * "Instruction TLB: 4-MB pages, 4-way set associative, 4 entries"
166 */
167 *itlb_4MB = (struct cpuinfo_tlb) {
168 .entries = 4,
169 .associativity = 4,
170 .pages = CPUINFO_PAGE_SIZE_4MB,
171 };
172 break;
173 case 0x0C:
174 /*
175 * Intel ISA Reference:
176 * "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size"
177 * Application Note 485:
178 * "1st-level data cache: 16-KB, 4-way set associative, 32-byte line size"
179 */
180 cache->l1d = (struct cpuinfo_x86_cache) {
181 .size = 16 * 1024,
182 .associativity = 4,
183 .sets = 128,
184 .partitions = 1,
185 .line_size = 32,
186 };
187 break;
188 case 0x0D:
189 /*
190 * Intel ISA Reference:
191 * "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"
192 * Application Note 485:
193 * "1st-level Data Cache: 16-KB, 4-way set associative, 64-byte line size"
194 */
195 cache->l1d = (struct cpuinfo_x86_cache) {
196 .size = 16 * 1024,
197 .associativity = 4,
198 .sets = 64,
199 .partitions = 1,
200 .line_size = 64,
201 };
202 break;
203 case 0x0E:
204 /*
205 * Intel ISA Reference:
206 * "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size"
207 * Application Note 485:
208 * "1st-level Data Cache: 24-KB, 6-way set associative, 64-byte line size"
209 */
210 cache->l1d = (struct cpuinfo_x86_cache) {
211 .size = 24 * 1024,
212 .associativity = 6,
213 .sets = 64,
214 .partitions = 1,
215 .line_size = 64,
216 };
217 break;
218 case 0x1D:
219 /*
220 * Intel ISA Reference:
221 * "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size"
222 */
223 cache->l2 = (struct cpuinfo_x86_cache) {
224 .size = 128 * 1024,
225 .associativity = 2,
226 .sets = 1024,
227 .partitions = 1,
228 .line_size = 64,
229 .flags = CPUINFO_CACHE_INCLUSIVE,
230 };
231 case 0x21:
232 /*
233 * Intel ISA Reference:
234 * "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size"
235 * Application Note 485:
236 * "2nd-level cache: 256-KB, 8-way set associative, 64-byte line size"
237 */
238 cache->l2 = (struct cpuinfo_x86_cache) {
239 .size = 256 * 1024,
240 .associativity = 8,
241 .sets = 512,
242 .partitions = 1,
243 .line_size = 64,
244 .flags = CPUINFO_CACHE_INCLUSIVE,
245 };
246 break;
247 case 0x22:
248 /*
249 * Intel ISA Reference:
250 * "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector"
251 * Application Note 485:
252 * "3rd-level cache: 512-KB, 4-way set associative, sectored cache, 64-byte line size"
253 */
254 cache->l3 = (struct cpuinfo_x86_cache) {
255 .size = 512 * 1024,
256 .associativity = 4,
257 .sets = 2048,
258 .partitions = 1,
259 .line_size = 64,
260 .flags = CPUINFO_CACHE_INCLUSIVE,
261 };
262 break;
263 case 0x23:
264 /*
265 * Intel ISA Reference:
266 * "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"
267 * Application Note 485:
268 * "3rd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size"
269 */
270 cache->l3 = (struct cpuinfo_x86_cache) {
271 .size = 1024 * 1024,
272 .associativity = 8,
273 .sets = 2048,
274 .partitions = 1,
275 .line_size = 64,
276 .flags = CPUINFO_CACHE_INCLUSIVE,
277 };
278 break;
279 case 0x24:
280 /*
281 * Intel ISA Reference:
282 * "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size"
283 */
284 cache->l2 = (struct cpuinfo_x86_cache) {
285 .size = 1024 * 1024,
286 .associativity = 16,
287 .sets = 1024,
288 .partitions = 1,
289 .line_size = 64,
290 .flags = CPUINFO_CACHE_INCLUSIVE,
291 };
292 break;
293 case 0x25:
294 /*
295 * Intel ISA Reference:
296 * "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"
297 * Application Note 485:
298 * "3rd-level cache: 2-MB, 8-way set associative, sectored cache, 64-byte line size"
299 */
300 cache->l3 = (struct cpuinfo_x86_cache) {
301 .size = 2 * 1024 * 1024,
302 .associativity = 8,
303 .sets = 4096,
304 .partitions = 1,
305 .line_size = 64,
306 .flags = CPUINFO_CACHE_INCLUSIVE,
307 };
308 break;
309 case 0x29:
310 /*
311 * Intel ISA Reference:
312 * "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"
313 * Application Note 485:
314 * "3rd-level cache: 4-MB, 8-way set associative, sectored cache, 64-byte line size"
315 */
316 cache->l3 = (struct cpuinfo_x86_cache) {
317 .size = 4 * 1024 * 1024,
318 .associativity = 8,
319 .sets = 8192,
320 .partitions = 1,
321 .line_size = 64,
322 .flags = CPUINFO_CACHE_INCLUSIVE,
323 };
324 break;
325 case 0x2C:
326 /*
327 * Intel ISA Reference:
328 * "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size"
329 * Application Note 485:
330 * "1st-level data cache: 32-KB, 8-way set associative, 64-byte line size"
331 */
332 cache->l1d = (struct cpuinfo_x86_cache) {
333 .size = 32 * 1024,
334 .associativity = 8,
335 .sets = 64,
336 .partitions = 1,
337 .line_size = 64,
338 };
339 break;
340 case 0x30:
341 /*
342 * Intel ISA Reference:
343 * "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size"
344 * Application Note 485:
345 * "1st-level instruction cache: 32-KB, 8-way set associative, 64-byte line size"
346 */
347 cache->l1i = (struct cpuinfo_x86_cache) {
348 .size = 32 * 1024,
349 .associativity = 8,
350 .sets = 64,
351 .partitions = 1,
352 .line_size = 64,
353 };
354 break;
355 case 0x39:
356 /* Where does this come from? */
357 cache->l2 = (struct cpuinfo_x86_cache) {
358 .size = 128 * 1024,
359 .associativity = 4,
360 .sets = 512,
361 .partitions = 1,
362 .line_size = 64,
363 .flags = CPUINFO_CACHE_INCLUSIVE,
364 };
365 break;
366 case 0x3A:
367 /* Where does this come from? */
368 cache->l2 = (struct cpuinfo_x86_cache) {
369 .size = 192 * 1024,
370 .associativity = 6,
371 .sets = 512,
372 .partitions = 1,
373 .line_size = 64,
374 .flags = CPUINFO_CACHE_INCLUSIVE,
375 };
376 break;
377 case 0x3B:
378 /* Where does this come from? */
379 cache->l2 = (struct cpuinfo_x86_cache) {
380 .size = 128 * 1024,
381 .associativity = 2,
382 .sets = 1024,
383 .partitions = 1,
384 .line_size = 64,
385 .flags = CPUINFO_CACHE_INCLUSIVE,
386 };
387 break;
388 case 0x3C:
389 /* Where does this come from? */
390 cache->l2 = (struct cpuinfo_x86_cache) {
391 .size = 256 * 1024,
392 .associativity = 4,
393 .sets = 1024,
394 .partitions = 1,
395 .line_size = 64,
396 .flags = CPUINFO_CACHE_INCLUSIVE,
397 };
398 break;
399 case 0x3D:
400 /* Where does this come from? */
401 cache->l2 = (struct cpuinfo_x86_cache) {
402 .size = 384 * 1024,
403 .associativity = 6,
404 .sets = 1024,
405 .partitions = 1,
406 .line_size = 64,
407 .flags = CPUINFO_CACHE_INCLUSIVE,
408 };
409 break;
410 case 0x3E:
411 /* Where does this come from? */
412 cache->l2 = (struct cpuinfo_x86_cache) {
413 .size = 512 * 1024,
414 .associativity = 4,
415 .sets = 2048,
416 .partitions = 1,
417 .line_size = 64,
418 .flags = CPUINFO_CACHE_INCLUSIVE,
419 };
420 break;
421 case 0x40:
422 /*
423 * Intel ISA Reference:
424 * "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache"
425 * Application Note 485:
426 * "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache"
427 */
428 break;
429 case 0x41:
430 /*
431 * Intel ISA Reference:
432 * "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size"
433 * Application Note 485:
434 * "2nd-level cache: 128-KB, 4-way set associative, 32-byte line size"
435 */
436 cache->l2 = (struct cpuinfo_x86_cache) {
437 .size = 128 * 1024,
438 .associativity = 4,
439 .sets = 1024,
440 .partitions = 1,
441 .line_size = 32,
442 .flags = CPUINFO_CACHE_INCLUSIVE,
443 };
444 break;
445 case 0x42:
446 /*
447 * Intel ISA Reference:
448 * "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size"
449 * Application Note 485:
450 * "2nd-level cache: 256-KB, 4-way set associative, 32-byte line size"
451 */
452 cache->l2 = (struct cpuinfo_x86_cache) {
453 .size = 256 * 1024,
454 .associativity = 4,
455 .sets = 2048,
456 .partitions = 1,
457 .line_size = 32,
458 .flags = CPUINFO_CACHE_INCLUSIVE,
459 };
460 break;
461 case 0x43:
462 /*
463 * Intel ISA Reference:
464 * "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size"
465 * Application Note 485:
466 * "2nd-level cache: 512-KB, 4-way set associative, 32-byte line size"
467 */
468 cache->l2 = (struct cpuinfo_x86_cache) {
469 .size = 512 * 1024,
470 .associativity = 4,
471 .sets = 4096,
472 .partitions = 1,
473 .line_size = 32,
474 .flags = CPUINFO_CACHE_INCLUSIVE,
475 };
476 break;
477 case 0x44:
478 /*
479 * Intel ISA Reference:
480 * "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size"
481 * Application Note 485:
482 * "2nd-level cache: 1-MB, 4-way set associative, 32-byte line size"
483 */
484 cache->l2 = (struct cpuinfo_x86_cache) {
485 .size = 1024 * 1024,
486 .associativity = 4,
487 .sets = 8192,
488 .partitions = 1,
489 .line_size = 32,
490 .flags = CPUINFO_CACHE_INCLUSIVE,
491 };
492 break;
493 case 0x45:
494 /*
495 * Intel ISA Reference:
496 * "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size"
497 * Application Note 485:
498 * "2nd-level cache: 2-MB, 4-way set associative, 32-byte line size"
499 */
500 cache->l2 = (struct cpuinfo_x86_cache) {
501 .size = 2 * 1024 * 1024,
502 .associativity = 4,
503 .sets = 16384,
504 .partitions = 1,
505 .line_size = 32,
506 .flags = CPUINFO_CACHE_INCLUSIVE,
507 };
508 break;
509 case 0x46:
510 /*
511 * Intel ISA Reference:
512 * "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size"
513 * Application Note 485:
514 * "3rd-level cache: 4-MB, 4-way set associative, 64-byte line size"
515 */
516 cache->l3 = (struct cpuinfo_x86_cache) {
517 .size = 4 * 1024 * 1024,
518 .associativity = 4,
519 .sets = 16384,
520 .partitions = 1,
521 .line_size = 64,
522 .flags = CPUINFO_CACHE_INCLUSIVE,
523 };
524 break;
525 case 0x47:
526 /*
527 * Intel ISA Reference:
528 * "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size"
529 * Application Note 485:
530 * "3rd-level cache: 8-MB, 8-way set associative, 64-byte line size"
531 */
532 cache->l3 = (struct cpuinfo_x86_cache) {
533 .size = 8 * 1024 * 1024,
534 .associativity = 8,
535 .sets = 16384,
536 .partitions = 1,
537 .line_size = 64,
538 .flags = CPUINFO_CACHE_INCLUSIVE,
539 };
540 break;
541 case 0x48:
542 /*
543 * Intel ISA Reference:
544 * "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size"
545 * Application Note 485:
546 * "2nd-level cache: 3-MB, 12-way set associative, 64-byte line size, unified on-die"
547 */
548 cache->l2 = (struct cpuinfo_x86_cache) {
549 .size = 3 * 1024 * 1024,
550 .associativity = 12,
551 .sets = 4096,
552 .partitions = 1,
553 .line_size = 64,
554 .flags = CPUINFO_CACHE_INCLUSIVE,
555 };
556 break;
557 case 0x49:
558 /*
559 * Intel ISA Reference:
560 * "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP,
561 * Family 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"
562 * Application Note 485:
563 * "3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP,
564 * Family 0Fh, Model 06h)
565 * 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size"
566 */
567 if ((vendor == cpuinfo_vendor_intel) && (model_info->model == 0x06) && (model_info->family == 0x0F)) {
568 cache->l3 = (struct cpuinfo_x86_cache) {
569 .size = 4 * 1024 * 1024,
570 .associativity = 16,
571 .sets = 4096,
572 .partitions = 1,
573 .line_size = 64,
574 .flags = CPUINFO_CACHE_INCLUSIVE,
575 };
576 } else {
577 cache->l2 = (struct cpuinfo_x86_cache) {
578 .size = 4 * 1024 * 1024,
579 .associativity = 16,
580 .sets = 4096,
581 .partitions = 1,
582 .line_size = 64,
583 .flags = CPUINFO_CACHE_INCLUSIVE,
584 };
585 }
586 break;
587 case 0x4A:
588 /*
589 * Intel ISA Reference:
590 * "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size"
591 * Application Note 485:
592 * "3rd-level cache: 6-MB, 12-way set associative, 64-byte line size"
593 */
594 cache->l3 = (struct cpuinfo_x86_cache) {
595 .size = 6 * 1024 * 1024,
596 .associativity = 12,
597 .sets = 8192,
598 .partitions = 1,
599 .line_size = 64,
600 .flags = CPUINFO_CACHE_INCLUSIVE,
601 };
602 break;
603 case 0x4B:
604 /*
605 * Intel ISA Reference:
606 * "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size"
607 * Application Note 485:
608 * "3rd-level cache: 8-MB, 16-way set associative, 64-byte line size"
609 */
610 cache->l3 = (struct cpuinfo_x86_cache) {
611 .size = 8 * 1024 * 1024,
612 .associativity = 16,
613 .sets = 8192,
614 .partitions = 1,
615 .line_size = 64,
616 .flags = CPUINFO_CACHE_INCLUSIVE,
617 };
618 break;
619 case 0x4C:
620 /*
621 * Intel ISA Reference:
622 * "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size"
623 * Application Note 485:
624 * "3rd-level cache: 12-MB, 12-way set associative, 64-byte line size"
625 */
626 cache->l3 = (struct cpuinfo_x86_cache) {
627 .size = 12 * 1024 * 1024,
628 .associativity = 12,
629 .sets = 16384,
630 .partitions = 1,
631 .line_size = 64,
632 .flags = CPUINFO_CACHE_INCLUSIVE,
633 };
634 break;
635 case 0x4D:
636 /*
637 * Intel ISA Reference:
638 * "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size"
639 * Application Note 485:
640 * "3rd-level cache: 16-MB, 16-way set associative, 64-byte line size"
641 */
642 cache->l3 = (struct cpuinfo_x86_cache) {
643 .size = 16 * 1024 * 1024,
644 .associativity = 16,
645 .sets = 16384,
646 .partitions = 1,
647 .line_size = 64,
648 .flags = CPUINFO_CACHE_INCLUSIVE,
649 };
650 break;
651 case 0x4E:
652 /*
653 * Intel ISA Reference:
654 * "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size"
655 * Application Note 485:
656 * "2nd-level cache: 6-MB, 24-way set associative, 64-byte line size"
657 */
658 cache->l2 = (struct cpuinfo_x86_cache) {
659 .size = 6 * 1024 * 1024,
660 .associativity = 24,
661 .sets = 4096,
662 .partitions = 1,
663 .line_size = 64,
664 .flags = CPUINFO_CACHE_INCLUSIVE,
665 };
666 break;
667 case 0x4F:
668 /*
669 * Intel ISA Reference:
670 * "Instruction TLB: 4 KByte pages, 32 entries"
671 * Application Note 485:
672 * "Instruction TLB: 4-KB pages, 32 entries"
673 */
674 *itlb_4KB = (struct cpuinfo_tlb) {
675 .entries = 32,
676 /* Assume full associativity from nearby entries: manual lacks detail */
677 .associativity = 32,
678 .pages = CPUINFO_PAGE_SIZE_4KB,
679 };
680 break;
681 case 0x50:
682 /*
683 * Intel ISA Reference:
684 * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries"
685 * Application Note 485:
686 * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries"
687 */
688 *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) {
689 .entries = 64,
690 .associativity = 64,
691 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
692 };
693 break;
694 case 0x51:
695 /*
696 * Intel ISA Reference:
697 * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries"
698 * Application Note 485:
699 * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries"
700 */
701 *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) {
702 .entries = 128,
703 .associativity = 128,
704 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
705 };
706 break;
707 case 0x52:
708 /*
709 * Intel ISA Reference:
710 * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries"
711 * Application Note 485:
712 * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 256 entries"
713 */
714 *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) {
715 .entries = 256,
716 .associativity = 256,
717 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
718 };
719 break;
720 case 0x55:
721 /*
722 * Intel ISA Reference:
723 * "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries"
724 * Application Note 485:
725 * "Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries"
726 */
727 *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) {
728 .entries = 7,
729 .associativity = 7,
730 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
731 };
732 break;
733 case 0x56:
734 /*
735 * Intel ISA Reference:
736 * "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries"
737 * Application Note 485:
738 * "L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries"
739 */
740 *dtlb0_4MB = (struct cpuinfo_tlb) {
741 .entries = 16,
742 .associativity = 4,
743 .pages = CPUINFO_PAGE_SIZE_4MB,
744 };
745 break;
746 case 0x57:
747 /*
748 * Intel ISA Reference:
749 * "Data TLB0: 4 KByte pages, 4-way associative, 16 entries"
750 * Application Note 485:
751 * "L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries"
752 */
753 *dtlb0_4KB = (struct cpuinfo_tlb) {
754 .entries = 16,
755 .associativity = 4,
756 .pages = CPUINFO_PAGE_SIZE_4KB,
757 };
758 break;
759 case 0x59:
760 /*
761 * Intel ISA Reference:
762 * "Data TLB0: 4 KByte pages, fully associative, 16 entries"
763 * Application Note 485:
764 * "Data TLB0: 4-KB pages, fully associative, 16 entries"
765 */
766 *dtlb0_4KB = (struct cpuinfo_tlb) {
767 .entries = 16,
768 .associativity = 16,
769 .pages = CPUINFO_PAGE_SIZE_4KB,
770 };
771 break;
772 case 0x5A:
773 /*
774 * Intel ISA Reference:
775 * "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries"
776 * Application Note 485:
777 * "Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries"
778 */
779 *dtlb0_2MB = *dtlb0_4MB = (struct cpuinfo_tlb) {
780 .entries = 32,
781 .associativity = 4,
782 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
783 };
784 break;
785 case 0x5B:
786 /*
787 * Intel ISA Reference:
788 * "Data TLB: 4 KByte and 4 MByte pages, 64 entries"
789 * Application Note 485:
790 * "Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries"
791 */
792 *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) {
793 .entries = 64,
794 .associativity = 64,
795 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB,
796 };
797 break;
798 case 0x5C:
799 /*
800 * Intel ISA Reference:
801 * "Data TLB: 4 KByte and 4 MByte pages, 128 entries"
802 * Application Note 485:
803 * "Data TLB: 4-KB or 4-MB pages, fully associative, 128 entries"
804 */
805 *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) {
806 .entries = 128,
807 .associativity = 128,
808 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB,
809 };
810 break;
811 case 0x5D:
812 /*
813 * Intel ISA Reference:
814 * "Data TLB: 4 KByte and 4 MByte pages, 256 entries"
815 * Application Note 485:
816 * "Data TLB: 4-KB or 4-MB pages, fully associative, 256 entries"
817 */
818 *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) {
819 .entries = 256,
820 .associativity = 256,
821 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB,
822 };
823 break;
824 case 0x60:
825 /*
826 * Application Note 485:
827 * "1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size"
828 */
829 cache->l1d = (struct cpuinfo_x86_cache) {
830 .size = 16 * 1024,
831 .associativity = 8,
832 .sets = 32,
833 .partitions = 1,
834 .line_size = 64,
835 };
836 break;
837 case 0x61:
838 /*
839 * Intel ISA Reference:
840 * "Instruction TLB: 4 KByte pages, fully associative, 48 entries"
841 */
842 *itlb_4KB = (struct cpuinfo_tlb) {
843 .entries = 48,
844 .associativity = 48,
845 .pages = CPUINFO_PAGE_SIZE_4KB,
846 };
847 break;
848 case 0x63:
849 /*
850 * Intel ISA Reference:
851 * "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and
852 * a separate array with 1 GByte pages, 4-way set associative, 4 entries"
853 */
854 *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) {
855 .entries = 32,
856 .associativity = 4,
857 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
858 };
859 *dtlb_1GB = (struct cpuinfo_tlb) {
860 .entries = 4,
861 .associativity = 4,
862 .pages = CPUINFO_PAGE_SIZE_1GB,
863 };
864 break;
865 case 0x64:
866 /*
867 * Intel ISA Reference:
868 * "Data TLB: 4 KByte pages, 4-way set associative, 512 entries"
869 *
870 */
871 *dtlb_4KB = (struct cpuinfo_tlb) {
872 .entries = 512,
873 .associativity = 4,
874 .pages = CPUINFO_PAGE_SIZE_4KB,
875 };
876 break;
877 case 0x66:
878 /*
879 * Application Note 485:
880 * "1st-level data cache: 8-KB, 4-way set associative, sectored cache, 64-byte line size"
881 */
882 cache->l1d = (struct cpuinfo_x86_cache) {
883 .size = 8 * 1024,
884 .associativity = 4,
885 .sets = 32,
886 .partitions = 1,
887 .line_size = 64,
888 };
889 break;
890 case 0x67:
891 /*
892 * Application Note 485:
893 * "1st-level data cache: 16-KB, 4-way set associative, sectored cache, 64-byte line size"
894 */
895 cache->l1d = (struct cpuinfo_x86_cache) {
896 .size = 16 * 1024,
897 .associativity = 4,
898 .sets = 64,
899 .partitions = 1,
900 .line_size = 64,
901 };
902 break;
903 case 0x68:
904 /*
905 * Application Note 485:
906 * "1st-level data cache: 32-KB, 4 way set associative, sectored cache, 64-byte line size"
907 */
908 cache->l1d = (struct cpuinfo_x86_cache) {
909 .size = 32 * 1024,
910 .associativity = 4,
911 .sets = 128,
912 .partitions = 1,
913 .line_size = 64,
914 };
915 break;
916 case 0x6A:
917 /*
918 * Intel ISA Reference:
919 * "uTLB: 4 KByte pages, 8-way set associative, 64 entries"
920 */
921
922 /* uTLB is, an fact, a normal 1-level DTLB on Silvermont & Knoghts Landing */
923 *dtlb_4KB = (struct cpuinfo_tlb) {
924 .entries = 64,
925 .associativity = 8,
926 .pages = CPUINFO_PAGE_SIZE_4KB,
927 };
928 break;
929 case 0x6B:
930 /*
931 * Intel ISA Reference:
932 * "DTLB: 4 KByte pages, 8-way set associative, 256 entries"
933 */
934 *dtlb_4KB = (struct cpuinfo_tlb) {
935 .entries = 256,
936 .associativity = 8,
937 .pages = CPUINFO_PAGE_SIZE_4KB,
938 };
939 break;
940 case 0x6C:
941 /*
942 * Intel ISA Reference:
943 * "DTLB: 2M/4M pages, 8-way set associative, 128 entries"
944 */
945 *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) {
946 .entries = 128,
947 .associativity = 8,
948 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
949 };
950 break;
951 case 0x6D:
952 /*
953 * Intel ISA Reference:
954 * "DTLB: 1 GByte pages, fully associative, 16 entries"
955 */
956 *dtlb_1GB = (struct cpuinfo_tlb) {
957 .entries = 16,
958 .associativity = 16,
959 .pages = CPUINFO_PAGE_SIZE_1GB,
960 };
961 break;
962 case 0x70:
963 /*
964 * Intel ISA Reference:
965 * "Trace cache: 12 K-uop, 8-way set associative"
966 * Application Note 485:
967 * "Trace cache: 12K-uops, 8-way set associative"
968 * Cyrix CPU Detection Guide and Geode GX1 Processor Series:
969 * "TLB, 32 entries, 4-way set associative, 4K-Byte Pages"
970 */
971 switch (vendor) {
972 #if CPUINFO_ARCH_X86
973 case cpuinfo_vendor_cyrix:
974 case cpuinfo_vendor_nsc:
975 *dtlb_4KB = *itlb_4KB = (struct cpuinfo_tlb) {
976 .entries = 32,
977 .associativity = 4,
978 .pages = CPUINFO_PAGE_SIZE_4KB,
979 };
980 break;
981 #endif /* CPUINFO_ARCH_X86 */
982 default:
983 cache->trace = (struct cpuinfo_trace_cache) {
984 .uops = 12 * 1024,
985 .associativity = 8,
986 };
987 }
988 break;
989 case 0x71:
990 /*
991 * Intel ISA Reference:
992 * "Trace cache: 16 K-uop, 8-way set associative"
993 * Application Note 485:
994 * "Trace cache: 16K-uops, 8-way set associative"
995 */
996 cache->trace = (struct cpuinfo_trace_cache) {
997 .uops = 16 * 1024,
998 .associativity = 8,
999 };
1000 break;
1001 case 0x72:
1002 /*
1003 * Intel ISA Reference:
1004 * "Trace cache: 32 K-μop, 8-way set associative"
1005 * Application Note 485:
1006 * "Trace cache: 32K-uops, 8-way set associative"
1007 */
1008 cache->trace = (struct cpuinfo_trace_cache) {
1009 .uops = 32 * 1024,
1010 .associativity = 8,
1011 };
1012 break;
1013 case 0x73:
1014 /* Where does this come from? */
1015 cache->trace = (struct cpuinfo_trace_cache) {
1016 .uops = 64 * 1024,
1017 .associativity = 8,
1018 };
1019 break;
1020 case 0x76:
1021 /*
1022 * Intel ISA Reference:
1023 * "Instruction TLB: 2M/4M pages, fully associative, 8 entries"
1024 * Application Note 485:
1025 * "Instruction TLB: 2M/4M pages, fully associative, 8 entries"
1026 */
1027 *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) {
1028 .entries = 8,
1029 .associativity = 8,
1030 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
1031 };
1032 break;
1033 case 0x78:
1034 /*
1035 * Intel ISA Reference:
1036 * "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size"
1037 * Application Note 485:
1038 * "2nd-level cache: 1-MB, 4-way set associative, 64-byte line size"
1039 */
1040 cache->l2 = (struct cpuinfo_x86_cache) {
1041 .size = 1024 * 1024,
1042 .associativity = 4,
1043 .sets = 4096,
1044 .partitions = 1,
1045 .line_size = 64,
1046 .flags = CPUINFO_CACHE_INCLUSIVE,
1047 };
1048 break;
1049 case 0x79:
1050 /*
1051 * Intel ISA Reference:
1052 * "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"
1053 * Application Note 485:
1054 * "2nd-level cache: 128-KB, 8-way set associative, sectored cache, 64-byte line size"
1055 */
1056 cache->l2 = (struct cpuinfo_x86_cache) {
1057 .size = 128 * 1024,
1058 .associativity = 8,
1059 .sets = 256,
1060 .partitions = 1,
1061 .line_size = 64,
1062 .flags = CPUINFO_CACHE_INCLUSIVE,
1063 };
1064 break;
1065 case 0x7A:
1066 /*
1067 * Intel ISA Reference:
1068 * "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"
1069 * Application Note 485:
1070 * "2nd-level cache: 256-KB, 8-way set associative, sectored cache, 64-byte line size"
1071 */
1072 cache->l2 = (struct cpuinfo_x86_cache) {
1073 .size = 256 * 1024,
1074 .associativity = 8,
1075 .sets = 512,
1076 .partitions = 1,
1077 .line_size = 64,
1078 .flags = CPUINFO_CACHE_INCLUSIVE,
1079 };
1080 break;
1081 case 0x7B:
1082 /*
1083 * Intel ISA Reference:
1084 * "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"
1085 * Application Note 485:
1086 * "2nd-level cache: 512-KB, 8-way set associative, sectored cache, 64-byte line size"
1087 */
1088 cache->l2 = (struct cpuinfo_x86_cache) {
1089 .size = 512 * 1024,
1090 .associativity = 8,
1091 .sets = 1024,
1092 .partitions = 1,
1093 .line_size = 64,
1094 .flags = CPUINFO_CACHE_INCLUSIVE,
1095 };
1096 break;
1097 case 0x7C:
1098 /*
1099 * Intel ISA Reference:
1100 * "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector"
1101 * Application Note 485:
1102 * "2nd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size"
1103 */
1104 cache->l2 = (struct cpuinfo_x86_cache) {
1105 .size = 1024 * 1024,
1106 .associativity = 8,
1107 .sets = 2048,
1108 .partitions = 1,
1109 .line_size = 64,
1110 .flags = CPUINFO_CACHE_INCLUSIVE,
1111 };
1112 break;
1113 case 0x7D:
1114 /*
1115 * Intel ISA Reference:
1116 * "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size"
1117 * Application Note 485:
1118 * "2nd-level cache: 2-MB, 8-way set associative, 64-byte line size"
1119 */
1120 cache->l2 = (struct cpuinfo_x86_cache) {
1121 .size = 2 * 1024 * 1024,
1122 .associativity = 8,
1123 .sets = 4096,
1124 .partitions = 1,
1125 .line_size = 64,
1126 .flags = CPUINFO_CACHE_INCLUSIVE,
1127 };
1128 break;
1129 case 0x7F:
1130 /*
1131 * Intel ISA Reference:
1132 * "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size"
1133 * Application Note 485:
1134 * "2nd-level cache: 512-KB, 2-way set associative, 64-byte line size"
1135 */
1136 cache->l2 = (struct cpuinfo_x86_cache) {
1137 .size = 512 * 1024,
1138 .associativity = 2,
1139 .sets = 4096,
1140 .partitions = 1,
1141 .line_size = 64,
1142 .flags = CPUINFO_CACHE_INCLUSIVE,
1143 };
1144 break;
1145 case 0x80:
1146 /*
1147 * Intel ISA Reference:
1148 * "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size"
1149 * Application Note 485:
1150 * "2nd-level cache: 512-KB, 8-way set associative, 64-byte line size"
1151 * Cyrix CPU Detection Guide and Geode GX1 Processor Series:
1152 * "Level 1 Cache, 16K, 4-way set associative, 16 Bytes/Line"
1153 */
1154 switch (vendor) {
1155 #if CPUINFO_ARCH_X86 && !defined(__ANDROID__)
1156 case cpuinfo_vendor_cyrix:
1157 case cpuinfo_vendor_nsc:
1158 cache->l1i = cache->l1d = (struct cpuinfo_x86_cache) {
1159 .size = 16 * 1024,
1160 .associativity = 4,
1161 .sets = 256,
1162 .partitions = 1,
1163 .line_size = 16,
1164 .flags = CPUINFO_CACHE_UNIFIED,
1165 };
1166 break;
1167 #endif /* CPUINFO_ARCH_X86 */
1168 default:
1169 cache->l2 = (struct cpuinfo_x86_cache) {
1170 .size = 512 * 1024,
1171 .associativity = 8,
1172 .sets = 1024,
1173 .partitions = 1,
1174 .line_size = 64,
1175 .flags = CPUINFO_CACHE_INCLUSIVE,
1176 };
1177 }
1178 break;
1179 case 0x82:
1180 /*
1181 * Intel ISA Reference:
1182 * "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size"
1183 * Application Note 485:
1184 * "2nd-level cache: 256-KB, 8-way set associative, 32-byte line size"
1185 */
1186 cache->l2 = (struct cpuinfo_x86_cache) {
1187 .size = 256 * 1024,
1188 .associativity = 4,
1189 .sets = 2048,
1190 .partitions = 1,
1191 .line_size = 32,
1192 .flags = CPUINFO_CACHE_INCLUSIVE,
1193 };
1194 break;
1195 case 0x83:
1196 /*
1197 * Intel ISA Reference:
1198 * "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size"
1199 * Application Note 485:
1200 * "2nd-level cache: 512-KB, 8-way set associative, 32-byte line size"
1201 */
1202 cache->l2 = (struct cpuinfo_x86_cache) {
1203 .size = 512 * 1024,
1204 .associativity = 8,
1205 .sets = 2048,
1206 .partitions = 1,
1207 .line_size = 32,
1208 .flags = CPUINFO_CACHE_INCLUSIVE,
1209 };
1210 break;
1211 case 0x84:
1212 /*
1213 * Intel ISA Reference:
1214 * "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size"
1215 * Application Note 485:
1216 * "2nd-level cache: 1-MB, 8-way set associative, 32-byte line size"
1217 */
1218 cache->l2 = (struct cpuinfo_x86_cache) {
1219 .size = 1024 * 1024,
1220 .associativity = 8,
1221 .sets = 4096,
1222 .partitions = 1,
1223 .line_size = 32,
1224 .flags = CPUINFO_CACHE_INCLUSIVE,
1225 };
1226 break;
1227 case 0x85:
1228 /*
1229 * Intel ISA Reference:
1230 * "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size"
1231 * Application Note 485:
1232 * "2nd-level cache: 2-MB, 8-way set associative, 32-byte line size"
1233 */
1234 cache->l2 = (struct cpuinfo_x86_cache) {
1235 .size = 2 * 1024 * 1024,
1236 .associativity = 8,
1237 .sets = 8192,
1238 .partitions = 1,
1239 .line_size = 32,
1240 .flags = CPUINFO_CACHE_INCLUSIVE,
1241 };
1242 break;
1243 case 0x86:
1244 /*
1245 * Intel ISA Reference:
1246 * "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size"
1247 * Application Note 485:
1248 * "2nd-level cache: 512-KB, 4-way set associative, 64-byte line size"
1249 */
1250 cache->l2 = (struct cpuinfo_x86_cache) {
1251 .size = 512 * 1024,
1252 .associativity = 4,
1253 .sets = 2048,
1254 .partitions = 1,
1255 .line_size = 64,
1256 .flags = CPUINFO_CACHE_INCLUSIVE,
1257 };
1258 break;
1259 case 0x87:
1260 /*
1261 * Intel ISA Reference:
1262 * "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size"
1263 * Application Note 485:
1264 * "2nd-level cache: 1-MB, 8-way set associative, 64-byte line size"
1265 */
1266 cache->l2 = (struct cpuinfo_x86_cache) {
1267 .size = 1024 * 1024,
1268 .associativity = 8,
1269 .sets = 2048,
1270 .partitions = 1,
1271 .line_size = 64,
1272 .flags = CPUINFO_CACHE_INCLUSIVE,
1273 };
1274 break;
1275 case 0xA0:
1276 /*
1277 * Intel ISA Reference:
1278 * "DTLB: 4k pages, fully associative, 32 entries"
1279 */
1280 *dtlb_4KB = (struct cpuinfo_tlb) {
1281 .entries = 32,
1282 .associativity = 32,
1283 .pages = CPUINFO_PAGE_SIZE_4KB,
1284 };
1285 break;
1286 case 0xB0:
1287 /*
1288 * Intel ISA Reference:
1289 * "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries"
1290 * Application Note 485:
1291 * "Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries"
1292 */
1293 *itlb_4KB = (struct cpuinfo_tlb) {
1294 .entries = 128,
1295 .associativity = 4,
1296 .pages = CPUINFO_PAGE_SIZE_4KB,
1297 };
1298 break;
1299 case 0xB1:
1300 /*
1301 * Intel ISA Reference:
1302 * "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries"
1303 * Application Note 485:
1304 * "Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries"
1305 */
1306 *itlb_2MB = (struct cpuinfo_tlb) {
1307 .entries = 8,
1308 .associativity = 4,
1309 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
1310 };
1311 *itlb_4MB = (struct cpuinfo_tlb) {
1312 .entries = 4,
1313 .associativity = 4,
1314 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
1315 };
1316 break;
1317 case 0xB2:
1318 /*
1319 * Intel ISA Reference:
1320 * "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries"
1321 * Application Note 485:
1322 * "Instruction TLB: 4-KB pages, 4-way set associative, 64 entries"
1323 */
1324 *itlb_4KB = (struct cpuinfo_tlb) {
1325 .entries = 64,
1326 .associativity = 4,
1327 .pages = CPUINFO_PAGE_SIZE_4KB,
1328 };
1329 break;
1330 case 0xB3:
1331 /*
1332 * Intel ISA Reference:
1333 * "Data TLB: 4 KByte pages, 4-way set associative, 128 entries"
1334 * Application Note 485:
1335 * "Data TLB: 4-KB Pages, 4-way set associative, 128 entries"
1336 */
1337 *dtlb_4KB = (struct cpuinfo_tlb) {
1338 .entries = 128,
1339 .associativity = 4,
1340 .pages = CPUINFO_PAGE_SIZE_4KB,
1341 };
1342 break;
1343 case 0xB4:
1344 /*
1345 * Intel ISA Reference:
1346 * "Data TLB1: 4 KByte pages, 4-way associative, 256 entries"
1347 * Application Note 485:
1348 * "Data TLB: 4-KB Pages, 4-way set associative, 256 entries"
1349 */
1350 *dtlb_4KB = (struct cpuinfo_tlb) {
1351 .entries = 256,
1352 .associativity = 4,
1353 .pages = CPUINFO_PAGE_SIZE_4KB,
1354 };
1355 break;
1356 case 0xB5:
1357 /*
1358 * Intel ISA Reference:
1359 * "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries"
1360 */
1361 *itlb_4KB = (struct cpuinfo_tlb) {
1362 .entries = 64,
1363 .associativity = 8,
1364 .pages = CPUINFO_PAGE_SIZE_4KB,
1365 };
1366 break;
1367 case 0xB6:
1368 /*
1369 * Intel ISA Reference:
1370 * "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries"
1371 */
1372 *itlb_4KB = (struct cpuinfo_tlb) {
1373 .entries = 128,
1374 .associativity = 8,
1375 .pages = CPUINFO_PAGE_SIZE_4KB,
1376 };
1377 break;
1378 case 0xBA:
1379 /*
1380 * Intel ISA Reference:
1381 * "Data TLB1: 4 KByte pages, 4-way associative, 64 entries"
1382 * Application Note 485:
1383 * "Data TLB: 4-KB Pages, 4-way set associative, 64 entries"
1384 */
1385 *itlb_4KB = (struct cpuinfo_tlb) {
1386 .entries = 64,
1387 .associativity = 4,
1388 .pages = CPUINFO_PAGE_SIZE_4KB,
1389 };
1390 break;
1391 case 0xC0:
1392 /*
1393 * Intel ISA Reference:
1394 * "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries"
1395 * Application Note 485:
1396 * "Data TLB: 4-KB or 4-MB Pages, 4-way set associative, 8 entries"
1397 */
1398 *itlb_4KB = *itlb_4MB = (struct cpuinfo_tlb) {
1399 .entries = 8,
1400 .associativity = 4,
1401 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB,
1402 };
1403 break;
1404 case 0xC1:
1405 /*
1406 * Intel ISA Reference:
1407 * "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries"
1408 */
1409 *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb) {
1410 .entries = 1024,
1411 .associativity = 8,
1412 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB,
1413 };
1414 break;
1415 case 0xC2:
1416 /*
1417 * Intel ISA Reference:
1418 * "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries"
1419 */
1420 *dtlb_4KB = *dtlb_2MB = (struct cpuinfo_tlb) {
1421 .entries = 16,
1422 .associativity = 4,
1423 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB,
1424 };
1425 break;
1426 case 0xC3:
1427 /*
1428 * Intel ISA Reference:
1429 * "Shared 2nd-Level TLB: 4 KByte/2 MByte pages, 6-way associative, 1536 entries.
1430 * Also 1GBbyte pages, 4-way, 16 entries."
1431 */
1432 *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb) {
1433 .entries = 1536,
1434 .associativity = 6,
1435 .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB,
1436 };
1437 *stlb2_1GB = (struct cpuinfo_tlb) {
1438 .entries = 16,
1439 .associativity = 4,
1440 .pages = CPUINFO_PAGE_SIZE_1GB,
1441 };
1442 break;
1443 case 0xC4:
1444 /*
1445 * Intel ISA Reference:
1446 * "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries"
1447 */
1448 *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) {
1449 .entries = 32,
1450 .associativity = 4,
1451 .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB,
1452 };
1453 break;
1454 case 0xCA:
1455 /*
1456 * Intel ISA Reference:
1457 * "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries"
1458 * Application Note 485:
1459 * "Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries"
1460 */
1461 *stlb2_4KB = (struct cpuinfo_tlb) {
1462 .entries = 512,
1463 .associativity = 4,
1464 .pages = CPUINFO_PAGE_SIZE_4KB,
1465 };
1466 break;
1467 case 0xD0:
1468 /*
1469 * Intel ISA Reference:
1470 * "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size"
1471 * Application Note 485:
1472 * "3rd-level cache: 512-kB, 4-way set associative, 64-byte line size"
1473 */
1474 cache->l3 = (struct cpuinfo_x86_cache) {
1475 .size = 512 * 1024,
1476 .associativity = 4,
1477 .sets = 2048,
1478 .partitions = 1,
1479 .line_size = 64,
1480 .flags = CPUINFO_CACHE_INCLUSIVE,
1481 };
1482 break;
1483 case 0xD1:
1484 /*
1485 * Intel ISA Reference:
1486 * "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size"
1487 * Application Note 485:
1488 * "3rd-level cache: 1-MB, 4-way set associative, 64-byte line size"
1489 */
1490 cache->l3 = (struct cpuinfo_x86_cache) {
1491 .size = 1024 * 1024,
1492 .associativity = 4,
1493 .sets = 4096,
1494 .partitions = 1,
1495 .line_size = 64,
1496 .flags = CPUINFO_CACHE_INCLUSIVE,
1497 };
1498 break;
1499 case 0xD2:
1500 /*
1501 * Intel ISA Reference:
1502 * "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size"
1503 * Application Note 485:
1504 * "3rd-level cache: 2-MB, 4-way set associative, 64-byte line size"
1505 */
1506 cache->l3 = (struct cpuinfo_x86_cache) {
1507 .size = 2 * 1024 * 2014,
1508 .associativity = 4,
1509 .sets = 8192,
1510 .partitions = 1,
1511 .line_size = 64,
1512 .flags = CPUINFO_CACHE_INCLUSIVE,
1513 };
1514 break;
1515 case 0xD6:
1516 /*
1517 * Intel ISA Reference:
1518 * "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size"
1519 * Application Note 485:
1520 * "3rd-level cache: 1-MB, 8-way set associative, 64-byte line size"
1521 */
1522 cache->l3 = (struct cpuinfo_x86_cache) {
1523 .size = 1024 * 1024,
1524 .associativity = 8,
1525 .sets = 2048,
1526 .partitions = 1,
1527 .line_size = 64,
1528 .flags = CPUINFO_CACHE_INCLUSIVE,
1529 };
1530 break;
1531 case 0xD7:
1532 /*
1533 * Intel ISA Reference:
1534 * "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size"
1535 * Application Note 485:
1536 * "3rd-level cache: 2-MB, 8-way set associative, 64-byte line size"
1537 */
1538 cache->l3 = (struct cpuinfo_x86_cache) {
1539 .size = 2 * 1024 * 1024,
1540 .associativity = 8,
1541 .sets = 4096,
1542 .partitions = 1,
1543 .line_size = 64,
1544 .flags = CPUINFO_CACHE_INCLUSIVE,
1545 };
1546 break;
1547 case 0xD8:
1548 /*
1549 * Intel ISA Reference:
1550 * "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size"
1551 * Application Note 485:
1552 * "3rd-level cache: 4-MB, 8-way set associative, 64-byte line size"
1553 */
1554 cache->l3 = (struct cpuinfo_x86_cache) {
1555 .size = 4 * 1024 * 1024,
1556 .associativity = 8,
1557 .sets = 8192,
1558 .partitions = 1,
1559 .line_size = 64,
1560 .flags = CPUINFO_CACHE_INCLUSIVE,
1561 };
1562 break;
1563 case 0xDC:
1564 /*
1565 * Intel ISA Reference:
1566 * "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size"
1567 * Application Note 485:
1568 * "3rd-level cache: 1.5-MB, 12-way set associative, 64-byte line size"
1569 */
1570 cache->l3 = (struct cpuinfo_x86_cache) {
1571 .size = 3 * 512 * 1024,
1572 .associativity = 12,
1573 .sets = 2048,
1574 .partitions = 1,
1575 .line_size = 64,
1576 .flags = CPUINFO_CACHE_INCLUSIVE,
1577 };
1578 break;
1579 case 0xDD:
1580 /*
1581 * Intel ISA Reference:
1582 * "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size"
1583 * Application Note 485:
1584 * "3rd-level cache: 3-MB, 12-way set associative, 64-byte line size"
1585 */
1586 cache->l3 = (struct cpuinfo_x86_cache) {
1587 .size = 3 * 1024 * 1024,
1588 .associativity = 12,
1589 .sets = 4096,
1590 .partitions = 1,
1591 .line_size = 64,
1592 .flags = CPUINFO_CACHE_INCLUSIVE,
1593 };
1594 break;
1595 case 0xDE:
1596 /*
1597 * Intel ISA Reference:
1598 * "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size"
1599 * Application Note 485:
1600 * "3rd-level cache: 6-MB, 12-way set associative, 64-byte line size"
1601 */
1602 cache->l3 = (struct cpuinfo_x86_cache) {
1603 .size = 6 * 1024 * 1024,
1604 .associativity = 12,
1605 .sets = 8192,
1606 .partitions = 1,
1607 .line_size = 64,
1608 .flags = CPUINFO_CACHE_INCLUSIVE,
1609 };
1610 break;
1611 case 0xE2:
1612 /*
1613 * Intel ISA Reference:
1614 * "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size"
1615 * Application Note 485:
1616 * "3rd-level cache: 2-MB, 16-way set associative, 64-byte line size"
1617 */
1618 cache->l3 = (struct cpuinfo_x86_cache) {
1619 .size = 2 * 1024 * 1024,
1620 .associativity = 16,
1621 .sets = 2048,
1622 .partitions = 1,
1623 .line_size = 64,
1624 .flags = CPUINFO_CACHE_INCLUSIVE,
1625 };
1626 break;
1627 case 0xE3:
1628 /*
1629 * Intel ISA Reference:
1630 * "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size"
1631 * Application Note 485:
1632 * "3rd-level cache: 4-MB, 16-way set associative, 64-byte line size"
1633 */
1634 cache->l3 = (struct cpuinfo_x86_cache) {
1635 .size = 4 * 1024 * 1024,
1636 .associativity = 16,
1637 .sets = 4096,
1638 .partitions = 1,
1639 .line_size = 64,
1640 .flags = CPUINFO_CACHE_INCLUSIVE,
1641 };
1642 break;
1643 case 0xE4:
1644 /*
1645 * Intel ISA Reference:
1646 * "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size"
1647 * Application Note 485:
1648 * "3rd-level cache: 8-MB, 16-way set associative, 64-byte line size"
1649 */
1650 cache->l3 = (struct cpuinfo_x86_cache) {
1651 .size = 8 * 1024 * 1024,
1652 .associativity = 16,
1653 .sets = 8192,
1654 .partitions = 1,
1655 .line_size = 64,
1656 .flags = CPUINFO_CACHE_INCLUSIVE,
1657 };
1658 break;
1659 case 0xEA:
1660 /*
1661 * Intel ISA Reference:
1662 * "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size"
1663 * Application Note 485:
1664 * "3rd-level cache: 12-MB, 24-way set associative, 64-byte line size"
1665 */
1666 cache->l3 = (struct cpuinfo_x86_cache) {
1667 .size = 12 * 1024 * 1024,
1668 .associativity = 24,
1669 .sets = 8192,
1670 .partitions = 1,
1671 .line_size = 64,
1672 .flags = CPUINFO_CACHE_INCLUSIVE,
1673 };
1674 break;
1675 case 0xEB:
1676 /*
1677 * Intel ISA Reference:
1678 * "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size"
1679 * Application Note 485:
1680 * "3rd-level cache: 18-MB, 24-way set associative, 64-byte line size"
1681 */
1682 cache->l3 = (struct cpuinfo_x86_cache) {
1683 .size = 18 * 1024 * 1024,
1684 .associativity = 24,
1685 .sets = 12288,
1686 .partitions = 1,
1687 .line_size = 64,
1688 .flags = CPUINFO_CACHE_INCLUSIVE,
1689 };
1690 break;
1691 case 0xEC:
1692 /*
1693 * Intel ISA Reference:
1694 * "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size"
1695 * Application Note 485:
1696 * "3rd-level cache: 24-MB, 24-way set associative, 64-byte line size"
1697 */
1698 cache->l3 = (struct cpuinfo_x86_cache) {
1699 .size = 24 * 1024 * 1024,
1700 .associativity = 24,
1701 .sets = 16384,
1702 .partitions = 1,
1703 .line_size = 64,
1704 .flags = CPUINFO_CACHE_INCLUSIVE,
1705 };
1706 break;
1707 case 0xF0:
1708 /*
1709 * Intel ISA Reference:
1710 * "64-Byte prefetching"
1711 * Application Note 485:
1712 * "64-byte Prefetching"
1713 */
1714 cache->prefetch_size = 64;
1715 break;
1716 case 0xF1:
1717 /*
1718 * Intel ISA Reference:
1719 * "128-Byte prefetching"
1720 * Application Note 485:
1721 * "128-byte Prefetching"
1722 */
1723 cache->prefetch_size = 128;
1724 break;
1725 }
1726 }
1727