1 // Copyright 2020 The Chromium OS Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // Implementation of an Intel ICH10 Input/Output Advanced Programmable Interrupt Controller
6 // See https://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf
7 // for a specification.
8
9 use std::fmt::{self, Display};
10
11 use super::IrqEvent;
12 use crate::bus::BusAccessInfo;
13 use crate::BusDevice;
14 use base::{error, warn, Error, Event, Result, Tube, TubeError};
15 use hypervisor::{
16 IoapicRedirectionTableEntry, IoapicState, MsiAddressMessage, MsiDataMessage, TriggerMode,
17 NUM_IOAPIC_PINS,
18 };
19 use vm_control::{VmIrqRequest, VmIrqResponse};
20
21 // ICH10 I/O APIC version: 0x20
22 const IOAPIC_VERSION_ID: u32 = 0x00000020;
23 pub const IOAPIC_BASE_ADDRESS: u64 = 0xfec00000;
24 // The Intel manual does not specify this size, but KVM uses it.
25 pub const IOAPIC_MEM_LENGTH_BYTES: u64 = 0x100;
26
27 // Constants for IOAPIC direct register offset.
28 const IOAPIC_REG_ID: u8 = 0x00;
29 const IOAPIC_REG_VERSION: u8 = 0x01;
30 const IOAPIC_REG_ARBITRATION_ID: u8 = 0x02;
31
32 // Register offsets
33 const IOREGSEL_OFF: u8 = 0x0;
34 const IOREGSEL_DUMMY_UPPER_32_BITS_OFF: u8 = 0x4;
35 const IOWIN_OFF: u8 = 0x10;
36 const IOEOIR_OFF: u8 = 0x40;
37
38 const IOWIN_SCALE: u8 = 0x2;
39
40 /// Given an IRQ and whether or not the selector should refer to the high bits, return a selector
41 /// suitable to use as an offset to read to/write from.
42 #[allow(dead_code)]
encode_selector_from_irq(irq: usize, is_high_bits: bool) -> u843 fn encode_selector_from_irq(irq: usize, is_high_bits: bool) -> u8 {
44 (irq as u8) * IOWIN_SCALE + IOWIN_OFF + (is_high_bits as u8)
45 }
46
47 /// Given an offset that was read from/written to, return a tuple of the relevant IRQ and whether
48 /// the offset refers to the high bits of that register.
decode_irq_from_selector(selector: u8) -> (usize, bool)49 fn decode_irq_from_selector(selector: u8) -> (usize, bool) {
50 (
51 ((selector - IOWIN_OFF) / IOWIN_SCALE) as usize,
52 selector & 1 != 0,
53 )
54 }
55
56 // The RTC needs special treatment to work properly for Windows (or other OSs that use tick
57 // stuffing). In order to avoid time drift, we need to guarantee that the correct number of RTC
58 // interrupts are injected into the guest. This hack essentialy treats RTC interrupts as level
59 // triggered, which allows the IOAPIC to be responsible for interrupt coalescing and allows the
60 // IOAPIC to pass back whether or not the interrupt was coalesced to the CMOS (which allows the
61 // CMOS to perform tick stuffing). This deviates from the IOAPIC spec in ways very similar to (but
62 // not exactly the same as) KVM's IOAPIC.
63 const RTC_IRQ: usize = 0x8;
64
65 pub struct Ioapic {
66 /// Number of supported IO-APIC inputs / redirection entries.
67 num_pins: usize,
68 /// ioregsel register. Used for selecting which entry of the redirect table to read/write.
69 ioregsel: u8,
70 /// ioapicid register. Bits 24 - 27 contain the APIC ID for this device.
71 ioapicid: u32,
72 /// Remote IRR for Edge Triggered Real Time Clock interrupts, which allows the CMOS to know when
73 /// one of its interrupts is being coalesced.
74 rtc_remote_irr: bool,
75 /// Outgoing irq events that are used to inject MSI interrupts.
76 out_events: Vec<Option<IrqEvent>>,
77 /// Events that should be triggered on an EOI. The outer Vec is indexed by GSI, and the inner
78 /// Vec is an unordered list of registered resample events for the GSI.
79 resample_events: Vec<Vec<Event>>,
80 /// Redirection settings for each irq line.
81 redirect_table: Vec<IoapicRedirectionTableEntry>,
82 /// Interrupt activation state.
83 interrupt_level: Vec<bool>,
84 /// Tube used to route MSI irqs.
85 irq_tube: Tube,
86 }
87
88 impl BusDevice for Ioapic {
debug_label(&self) -> String89 fn debug_label(&self) -> String {
90 "userspace IOAPIC".to_string()
91 }
92
read(&mut self, info: BusAccessInfo, data: &mut [u8])93 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) {
94 if data.len() > 8 || data.is_empty() {
95 warn!("IOAPIC: Bad read size: {}", data.len());
96 return;
97 }
98 if info.offset >= IOAPIC_MEM_LENGTH_BYTES {
99 warn!("IOAPIC: Bad read from {}", info);
100 }
101 let out = match info.offset as u8 {
102 IOREGSEL_OFF => self.ioregsel.into(),
103 IOREGSEL_DUMMY_UPPER_32_BITS_OFF => 0,
104 IOWIN_OFF => self.ioapic_read(),
105 IOEOIR_OFF => 0,
106 _ => {
107 warn!("IOAPIC: Bad read from {}", info);
108 return;
109 }
110 };
111 let out_arr = out.to_ne_bytes();
112 for i in 0..4 {
113 if i < data.len() {
114 data[i] = out_arr[i];
115 }
116 }
117 }
118
write(&mut self, info: BusAccessInfo, data: &[u8])119 fn write(&mut self, info: BusAccessInfo, data: &[u8]) {
120 if data.len() > 8 || data.is_empty() {
121 warn!("IOAPIC: Bad write size: {}", data.len());
122 return;
123 }
124 if info.offset >= IOAPIC_MEM_LENGTH_BYTES {
125 warn!("IOAPIC: Bad write to {}", info);
126 }
127 match info.offset as u8 {
128 IOREGSEL_OFF => self.ioregsel = data[0],
129 IOREGSEL_DUMMY_UPPER_32_BITS_OFF => {} // Ignored.
130 IOWIN_OFF => {
131 if data.len() != 4 {
132 warn!("IOAPIC: Bad write size for iowin: {}", data.len());
133 return;
134 }
135 let data_arr = [data[0], data[1], data[2], data[3]];
136 let val = u32::from_ne_bytes(data_arr);
137 self.ioapic_write(val);
138 }
139 IOEOIR_OFF => self.end_of_interrupt(data[0]),
140 _ => {
141 warn!("IOAPIC: Bad write to {}", info);
142 }
143 }
144 }
145 }
146
147 impl Ioapic {
new(irq_tube: Tube, num_pins: usize) -> Result<Ioapic>148 pub fn new(irq_tube: Tube, num_pins: usize) -> Result<Ioapic> {
149 let num_pins = num_pins.max(NUM_IOAPIC_PINS as usize);
150 let mut entry = IoapicRedirectionTableEntry::new();
151 entry.set_interrupt_mask(true);
152 Ok(Ioapic {
153 num_pins,
154 ioregsel: 0,
155 ioapicid: 0,
156 rtc_remote_irr: false,
157 out_events: (0..num_pins).map(|_| None).collect(),
158 resample_events: Vec::new(),
159 redirect_table: (0..num_pins).map(|_| entry.clone()).collect(),
160 interrupt_level: (0..num_pins).map(|_| false).collect(),
161 irq_tube,
162 })
163 }
164
get_ioapic_state(&self) -> IoapicState165 pub fn get_ioapic_state(&self) -> IoapicState {
166 // Convert vector of first NUM_IOAPIC_PINS active interrupts into an u32 value.
167 let level_bitmap = self
168 .interrupt_level
169 .iter()
170 .take(NUM_IOAPIC_PINS)
171 .rev()
172 .fold(0, |acc, &l| acc * 2 + l as u32);
173 let mut state = IoapicState {
174 base_address: IOAPIC_BASE_ADDRESS,
175 ioregsel: self.ioregsel,
176 ioapicid: self.ioapicid,
177 current_interrupt_level_bitmap: level_bitmap,
178 ..Default::default()
179 };
180 for (dst, src) in state
181 .redirect_table
182 .iter_mut()
183 .zip(self.redirect_table.iter())
184 {
185 *dst = *src;
186 }
187 state
188 }
189
set_ioapic_state(&mut self, state: &IoapicState)190 pub fn set_ioapic_state(&mut self, state: &IoapicState) {
191 self.ioregsel = state.ioregsel;
192 self.ioapicid = state.ioapicid & 0x0f00_0000;
193 for (src, dst) in state
194 .redirect_table
195 .iter()
196 .zip(self.redirect_table.iter_mut())
197 {
198 *dst = *src;
199 }
200 for (i, level) in self
201 .interrupt_level
202 .iter_mut()
203 .take(NUM_IOAPIC_PINS)
204 .enumerate()
205 {
206 *level = state.current_interrupt_level_bitmap & (1 << i) != 0;
207 }
208 }
209
register_resample_events(&mut self, resample_events: Vec<Vec<Event>>)210 pub fn register_resample_events(&mut self, resample_events: Vec<Vec<Event>>) {
211 self.resample_events = resample_events;
212 }
213
214 // The ioapic must be informed about EOIs in order to avoid sending multiple interrupts of the
215 // same type at the same time.
end_of_interrupt(&mut self, vector: u8)216 pub fn end_of_interrupt(&mut self, vector: u8) {
217 if self.redirect_table[RTC_IRQ].get_vector() == vector && self.rtc_remote_irr {
218 // Specifically clear RTC IRQ field
219 self.rtc_remote_irr = false;
220 }
221
222 for i in 0..self.num_pins {
223 if self.redirect_table[i].get_vector() == vector
224 && self.redirect_table[i].get_trigger_mode() == TriggerMode::Level
225 {
226 if self
227 .resample_events
228 .get(i)
229 .map_or(false, |events| !events.is_empty())
230 {
231 self.service_irq(i, false);
232 }
233
234 if let Some(resample_events) = self.resample_events.get(i) {
235 for resample_evt in resample_events {
236 resample_evt.write(1).unwrap();
237 }
238 }
239 self.redirect_table[i].set_remote_irr(false);
240 }
241 // There is an inherent race condition in hardware if the OS is finished processing an
242 // interrupt and a new interrupt is delivered between issuing an EOI and the EOI being
243 // completed. When that happens the ioapic is supposed to re-inject the interrupt.
244 if self.interrupt_level[i] {
245 self.service_irq(i, true);
246 }
247 }
248 }
249
service_irq(&mut self, irq: usize, level: bool) -> bool250 pub fn service_irq(&mut self, irq: usize, level: bool) -> bool {
251 let entry = &mut self.redirect_table[irq];
252
253 // De-assert the interrupt.
254 if !level {
255 self.interrupt_level[irq] = false;
256 return true;
257 }
258
259 // If it's an edge-triggered interrupt that's already high we ignore it.
260 if entry.get_trigger_mode() == TriggerMode::Edge && self.interrupt_level[irq] {
261 return false;
262 }
263
264 self.interrupt_level[irq] = true;
265
266 // Interrupts are masked, so don't inject.
267 if entry.get_interrupt_mask() {
268 return false;
269 }
270
271 // Level-triggered and remote irr is already active, so we don't inject a new interrupt.
272 // (Coalesce with the prior one(s)).
273 if entry.get_trigger_mode() == TriggerMode::Level && entry.get_remote_irr() {
274 return false;
275 }
276
277 // Coalesce RTC interrupt to make tick stuffing work.
278 if irq == RTC_IRQ && self.rtc_remote_irr {
279 return false;
280 }
281
282 let injected = match self.out_events.get(irq) {
283 Some(Some(evt)) => evt.event.write(1).is_ok(),
284 _ => false,
285 };
286
287 if entry.get_trigger_mode() == TriggerMode::Level && level && injected {
288 entry.set_remote_irr(true);
289 } else if irq == RTC_IRQ && injected {
290 self.rtc_remote_irr = true;
291 }
292
293 injected
294 }
295
ioapic_write(&mut self, val: u32)296 fn ioapic_write(&mut self, val: u32) {
297 match self.ioregsel {
298 IOAPIC_REG_VERSION => { /* read-only register */ }
299 IOAPIC_REG_ID => self.ioapicid = val & 0x0f00_0000,
300 IOAPIC_REG_ARBITRATION_ID => { /* read-only register */ }
301 _ => {
302 if self.ioregsel < IOWIN_OFF {
303 // Invalid write; ignore.
304 return;
305 }
306 let (index, is_high_bits) = decode_irq_from_selector(self.ioregsel);
307 if index >= self.num_pins {
308 // Invalid write; ignore.
309 return;
310 }
311
312 let entry = &mut self.redirect_table[index];
313 if is_high_bits {
314 entry.set(32, 32, val.into());
315 } else {
316 let before = *entry;
317 entry.set(0, 32, val.into());
318
319 // respect R/O bits.
320 entry.set_delivery_status(before.get_delivery_status());
321 entry.set_remote_irr(before.get_remote_irr());
322
323 // Clear remote_irr when switching to edge_triggered.
324 if entry.get_trigger_mode() == TriggerMode::Edge {
325 entry.set_remote_irr(false);
326 }
327
328 // NOTE: on pre-4.0 kernels, there's a race we would need to work around.
329 // "KVM: x86: ioapic: Fix level-triggered EOI and IOAPIC reconfigure race"
330 // is the fix for this.
331 }
332
333 if self.redirect_table[index].get_trigger_mode() == TriggerMode::Level
334 && self.interrupt_level[index]
335 && !self.redirect_table[index].get_interrupt_mask()
336 {
337 self.service_irq(index, true);
338 }
339
340 let mut address = MsiAddressMessage::new();
341 let mut data = MsiDataMessage::new();
342 let entry = &self.redirect_table[index];
343 address.set_destination_mode(entry.get_dest_mode());
344 address.set_destination_id(entry.get_dest_id());
345 address.set_always_0xfee(0xfee);
346 data.set_vector(entry.get_vector());
347 data.set_delivery_mode(entry.get_delivery_mode());
348 data.set_trigger(entry.get_trigger_mode());
349
350 let msi_address = address.get(0, 32);
351 let msi_data = data.get(0, 32);
352 if let Err(e) = self.setup_msi(index, msi_address, msi_data as u32) {
353 error!("IOAPIC failed to set up MSI for index {}: {}", index, e);
354 }
355 }
356 }
357 }
358
setup_msi( &mut self, index: usize, msi_address: u64, msi_data: u32, ) -> std::result::Result<(), IoapicError>359 fn setup_msi(
360 &mut self,
361 index: usize,
362 msi_address: u64,
363 msi_data: u32,
364 ) -> std::result::Result<(), IoapicError> {
365 if msi_data == 0 {
366 // During boot, Linux first configures all ioapic pins with msi_data == 0; the routes
367 // aren't yet assigned to devices and aren't usable. We skip MSI setup if msi_data is
368 // 0.
369 return Ok(());
370 }
371
372 // Allocate a GSI and event for the outgoing route, if we haven't already done it.
373 // The event will be used on the "outgoing" end of the ioapic to send an interrupt to the
374 // apics: when an incoming ioapic irq line gets signalled, the ioapic writes to the
375 // corresponding outgoing event. The GSI number is used to update the routing info (MSI
376 // data and addr) for the event. The GSI and event are allocated only once for each ioapic
377 // irq line, when the guest first sets up the ioapic with a valid route. If the guest
378 // later reconfigures an ioapic irq line, the same GSI and event are reused, and we change
379 // the GSI's route to the new MSI data+addr destination.
380 let gsi = if let Some(evt) = &self.out_events[index] {
381 evt.gsi
382 } else {
383 let event = Event::new().map_err(IoapicError::CreateEvent)?;
384 let request = VmIrqRequest::AllocateOneMsi { irqfd: event };
385 self.irq_tube
386 .send(&request)
387 .map_err(IoapicError::AllocateOneMsiSend)?;
388 match self
389 .irq_tube
390 .recv()
391 .map_err(IoapicError::AllocateOneMsiRecv)?
392 {
393 VmIrqResponse::AllocateOneMsi { gsi, .. } => {
394 self.out_events[index] = Some(IrqEvent {
395 gsi,
396 event: match request {
397 VmIrqRequest::AllocateOneMsi { irqfd } => irqfd,
398 _ => unreachable!(),
399 },
400 resample_event: None,
401 });
402 gsi
403 }
404 VmIrqResponse::Err(e) => return Err(IoapicError::AllocateOneMsi(e)),
405 _ => unreachable!(),
406 }
407 };
408
409 // Set the MSI route for the GSI. This controls which apic(s) get the interrupt when the
410 // ioapic's outgoing event is written, and various attributes of how the interrupt is
411 // delivered.
412 let request = VmIrqRequest::AddMsiRoute {
413 gsi,
414 msi_address,
415 msi_data,
416 };
417 self.irq_tube
418 .send(&request)
419 .map_err(IoapicError::AddMsiRouteSend)?;
420 if let VmIrqResponse::Err(e) = self.irq_tube.recv().map_err(IoapicError::AddMsiRouteRecv)? {
421 return Err(IoapicError::AddMsiRoute(e));
422 }
423 Ok(())
424 }
425
ioapic_read(&mut self) -> u32426 fn ioapic_read(&mut self) -> u32 {
427 match self.ioregsel {
428 IOAPIC_REG_VERSION => ((self.num_pins - 1) as u32) << 16 | IOAPIC_VERSION_ID,
429 IOAPIC_REG_ID | IOAPIC_REG_ARBITRATION_ID => self.ioapicid,
430 _ => {
431 if self.ioregsel < IOWIN_OFF {
432 // Invalid read; ignore and return 0.
433 0
434 } else {
435 let (index, is_high_bits) = decode_irq_from_selector(self.ioregsel);
436 if index < self.num_pins {
437 let offset = if is_high_bits { 32 } else { 0 };
438 self.redirect_table[index].get(offset, 32) as u32
439 } else {
440 !0 // Invalid index - return all 1s
441 }
442 }
443 }
444 }
445 }
446 }
447
448 #[derive(Debug)]
449 enum IoapicError {
450 AddMsiRoute(Error),
451 AddMsiRouteRecv(TubeError),
452 AddMsiRouteSend(TubeError),
453 AllocateOneMsi(Error),
454 AllocateOneMsiRecv(TubeError),
455 AllocateOneMsiSend(TubeError),
456 CreateEvent(Error),
457 }
458
459 impl Display for IoapicError {
460 #[remain::check]
fmt(&self, f: &mut fmt::Formatter) -> fmt::Result461 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
462 use self::IoapicError::*;
463
464 #[sorted]
465 match self {
466 AddMsiRoute(e) => write!(f, "AddMsiRoute failed: {}", e),
467 AddMsiRouteRecv(e) => write!(f, "failed to receive AddMsiRoute response: {}", e),
468 AddMsiRouteSend(e) => write!(f, "failed to send AddMsiRoute request: {}", e),
469 AllocateOneMsi(e) => write!(f, "AllocateOneMsi failed: {}", e),
470 AllocateOneMsiRecv(e) => write!(f, "failed to receive AllocateOneMsi response: {}", e),
471 AllocateOneMsiSend(e) => write!(f, "failed to send AllocateOneMsi request: {}", e),
472 CreateEvent(e) => write!(f, "failed to create event object: {}", e),
473 }
474 }
475 }
476
477 #[cfg(test)]
478 mod tests {
479 use super::*;
480 use hypervisor::{DeliveryMode, DeliveryStatus, DestinationMode};
481
482 const DEFAULT_VECTOR: u8 = 0x3a;
483 const DEFAULT_DESTINATION_ID: u8 = 0x5f;
484
new() -> Ioapic485 fn new() -> Ioapic {
486 let (_, irq_tube) = Tube::pair().unwrap();
487 Ioapic::new(irq_tube, NUM_IOAPIC_PINS).unwrap()
488 }
489
ioapic_bus_address(offset: u8) -> BusAccessInfo490 fn ioapic_bus_address(offset: u8) -> BusAccessInfo {
491 let offset = offset as u64;
492 BusAccessInfo {
493 offset,
494 address: IOAPIC_BASE_ADDRESS + offset,
495 id: 0,
496 }
497 }
498
set_up(trigger: TriggerMode) -> (Ioapic, usize)499 fn set_up(trigger: TriggerMode) -> (Ioapic, usize) {
500 let irq = NUM_IOAPIC_PINS - 1;
501 let ioapic = set_up_with_irq(irq, trigger);
502 (ioapic, irq)
503 }
504
set_up_with_irq(irq: usize, trigger: TriggerMode) -> Ioapic505 fn set_up_with_irq(irq: usize, trigger: TriggerMode) -> Ioapic {
506 let mut ioapic = self::new();
507 set_up_redirection_table_entry(&mut ioapic, irq, trigger);
508 ioapic.out_events[irq] = Some(IrqEvent {
509 gsi: NUM_IOAPIC_PINS as u32,
510 event: Event::new().unwrap(),
511 resample_event: None,
512 });
513 ioapic
514 }
515
read_reg(ioapic: &mut Ioapic, selector: u8) -> u32516 fn read_reg(ioapic: &mut Ioapic, selector: u8) -> u32 {
517 let mut data = [0; 4];
518 ioapic.write(ioapic_bus_address(IOREGSEL_OFF), &[selector]);
519 ioapic.read(ioapic_bus_address(IOWIN_OFF), &mut data);
520 u32::from_ne_bytes(data)
521 }
522
write_reg(ioapic: &mut Ioapic, selector: u8, value: u32)523 fn write_reg(ioapic: &mut Ioapic, selector: u8, value: u32) {
524 ioapic.write(ioapic_bus_address(IOREGSEL_OFF), &[selector]);
525 ioapic.write(ioapic_bus_address(IOWIN_OFF), &value.to_ne_bytes());
526 }
527
read_entry(ioapic: &mut Ioapic, irq: usize) -> IoapicRedirectionTableEntry528 fn read_entry(ioapic: &mut Ioapic, irq: usize) -> IoapicRedirectionTableEntry {
529 let mut entry = IoapicRedirectionTableEntry::new();
530 entry.set(
531 0,
532 32,
533 read_reg(ioapic, encode_selector_from_irq(irq, false)).into(),
534 );
535 entry.set(
536 32,
537 32,
538 read_reg(ioapic, encode_selector_from_irq(irq, true)).into(),
539 );
540 entry
541 }
542
write_entry(ioapic: &mut Ioapic, irq: usize, entry: IoapicRedirectionTableEntry)543 fn write_entry(ioapic: &mut Ioapic, irq: usize, entry: IoapicRedirectionTableEntry) {
544 write_reg(
545 ioapic,
546 encode_selector_from_irq(irq, false),
547 entry.get(0, 32) as u32,
548 );
549 write_reg(
550 ioapic,
551 encode_selector_from_irq(irq, true),
552 entry.get(32, 32) as u32,
553 );
554 }
555
set_up_redirection_table_entry(ioapic: &mut Ioapic, irq: usize, trigger_mode: TriggerMode)556 fn set_up_redirection_table_entry(ioapic: &mut Ioapic, irq: usize, trigger_mode: TriggerMode) {
557 let mut entry = IoapicRedirectionTableEntry::new();
558 entry.set_vector(DEFAULT_DESTINATION_ID);
559 entry.set_delivery_mode(DeliveryMode::Startup);
560 entry.set_delivery_status(DeliveryStatus::Pending);
561 entry.set_dest_id(DEFAULT_VECTOR);
562 entry.set_trigger_mode(trigger_mode);
563 write_entry(ioapic, irq, entry);
564 }
565
set_mask(ioapic: &mut Ioapic, irq: usize, mask: bool)566 fn set_mask(ioapic: &mut Ioapic, irq: usize, mask: bool) {
567 let mut entry = read_entry(ioapic, irq);
568 entry.set_interrupt_mask(mask);
569 write_entry(ioapic, irq, entry);
570 }
571
572 #[test]
write_read_ioregsel()573 fn write_read_ioregsel() {
574 let mut ioapic = self::new();
575 let data_write = [0x0f, 0xf0, 0x01, 0xff];
576 let mut data_read = [0; 4];
577
578 for i in 0..data_write.len() {
579 ioapic.write(ioapic_bus_address(IOREGSEL_OFF), &data_write[i..i + 1]);
580 ioapic.read(ioapic_bus_address(IOREGSEL_OFF), &mut data_read[i..i + 1]);
581 assert_eq!(data_write[i], data_read[i]);
582 }
583 }
584
585 // Verify that version register is actually read-only.
586 #[test]
write_read_ioaic_reg_version()587 fn write_read_ioaic_reg_version() {
588 let mut ioapic = self::new();
589 let before = read_reg(&mut ioapic, IOAPIC_REG_VERSION);
590 let data_write = !before;
591
592 write_reg(&mut ioapic, IOAPIC_REG_VERSION, data_write);
593 assert_eq!(read_reg(&mut ioapic, IOAPIC_REG_VERSION), before);
594 }
595
596 // Verify that only bits 27:24 of the IOAPICID are readable/writable.
597 #[test]
write_read_ioapic_reg_id()598 fn write_read_ioapic_reg_id() {
599 let mut ioapic = self::new();
600
601 write_reg(&mut ioapic, IOAPIC_REG_ID, 0x1f3e5d7c);
602 assert_eq!(read_reg(&mut ioapic, IOAPIC_REG_ID), 0x0f000000);
603 }
604
605 // Write to read-only register IOAPICARB.
606 #[test]
write_read_ioapic_arbitration_id()607 fn write_read_ioapic_arbitration_id() {
608 let mut ioapic = self::new();
609
610 let data_write_id = 0x1f3e5d7c;
611 let expected_result = 0x0f000000;
612
613 // Write to IOAPICID. This should also change IOAPICARB.
614 write_reg(&mut ioapic, IOAPIC_REG_ID, data_write_id);
615
616 // Read IOAPICARB
617 assert_eq!(
618 read_reg(&mut ioapic, IOAPIC_REG_ARBITRATION_ID),
619 expected_result
620 );
621
622 // Try to write to IOAPICARB and verify unchanged result.
623 write_reg(&mut ioapic, IOAPIC_REG_ARBITRATION_ID, !data_write_id);
624 assert_eq!(
625 read_reg(&mut ioapic, IOAPIC_REG_ARBITRATION_ID),
626 expected_result
627 );
628 }
629
630 #[test]
631 #[should_panic(expected = "index out of bounds: the len is 24 but the index is 24")]
service_invalid_irq()632 fn service_invalid_irq() {
633 let mut ioapic = self::new();
634 ioapic.service_irq(NUM_IOAPIC_PINS, false);
635 }
636
637 // Test a level triggered IRQ interrupt.
638 #[test]
service_level_irq()639 fn service_level_irq() {
640 let (mut ioapic, irq) = set_up(TriggerMode::Level);
641
642 // TODO(mutexlox): Check that interrupt is fired once.
643 ioapic.service_irq(irq, true);
644 ioapic.service_irq(irq, false);
645 }
646
647 #[test]
service_multiple_level_irqs()648 fn service_multiple_level_irqs() {
649 let (mut ioapic, irq) = set_up(TriggerMode::Level);
650 // TODO(mutexlox): Check that interrupt is fired twice.
651 ioapic.service_irq(irq, true);
652 ioapic.service_irq(irq, false);
653 ioapic.end_of_interrupt(DEFAULT_DESTINATION_ID);
654 ioapic.service_irq(irq, true);
655 }
656
657 // Test multiple level interrupts without an EOI and verify that only one interrupt is
658 // delivered.
659 #[test]
coalesce_multiple_level_irqs()660 fn coalesce_multiple_level_irqs() {
661 let (mut ioapic, irq) = set_up(TriggerMode::Level);
662
663 // TODO(mutexlox): Test that only one interrupt is delivered.
664 ioapic.service_irq(irq, true);
665 ioapic.service_irq(irq, false);
666 ioapic.service_irq(irq, true);
667 }
668
669 // Test multiple RTC interrupts without an EOI and verify that only one interrupt is delivered.
670 #[test]
coalesce_multiple_rtc_irqs()671 fn coalesce_multiple_rtc_irqs() {
672 let irq = RTC_IRQ;
673 let mut ioapic = set_up_with_irq(irq, TriggerMode::Edge);
674
675 // TODO(mutexlox): Verify that only one IRQ is delivered.
676 ioapic.service_irq(irq, true);
677 ioapic.service_irq(irq, false);
678 ioapic.service_irq(irq, true);
679 }
680
681 // Test that a level interrupt that has been coalesced is re-raised if a guest issues an
682 // EndOfInterrupt after the interrupt was coalesced while the line is still asserted.
683 #[test]
reinject_level_interrupt()684 fn reinject_level_interrupt() {
685 let (mut ioapic, irq) = set_up(TriggerMode::Level);
686
687 // TODO(mutexlox): Verify that only one IRQ is delivered.
688 ioapic.service_irq(irq, true);
689 ioapic.service_irq(irq, false);
690 ioapic.service_irq(irq, true);
691
692 // TODO(mutexlox): Verify that this last interrupt occurs as a result of the EOI, rather
693 // than in response to the last service_irq.
694 ioapic.end_of_interrupt(DEFAULT_DESTINATION_ID);
695 }
696
697 #[test]
service_edge_triggered_irq()698 fn service_edge_triggered_irq() {
699 let (mut ioapic, irq) = set_up(TriggerMode::Edge);
700
701 // TODO(mutexlox): Verify that one interrupt is delivered.
702 ioapic.service_irq(irq, true);
703 ioapic.service_irq(irq, true); // Repeated asserts before a deassert should be ignored.
704 ioapic.service_irq(irq, false);
705 }
706
707 // Verify that the state of an edge-triggered interrupt is properly tracked even when the
708 // interrupt is disabled.
709 #[test]
edge_trigger_unmask_test()710 fn edge_trigger_unmask_test() {
711 let (mut ioapic, irq) = set_up(TriggerMode::Edge);
712
713 // TODO(mutexlox): Expect an IRQ.
714
715 ioapic.service_irq(irq, true);
716
717 set_mask(&mut ioapic, irq, true);
718 ioapic.service_irq(irq, false);
719
720 // No interrupt triggered while masked.
721 ioapic.service_irq(irq, true);
722 ioapic.service_irq(irq, false);
723
724 set_mask(&mut ioapic, irq, false);
725
726 // TODO(mutexlox): Expect another interrupt.
727 // Interrupt triggered while unmasked, even though when it was masked the level was high.
728 ioapic.service_irq(irq, true);
729 ioapic.service_irq(irq, false);
730 }
731
732 // Verify that a level-triggered interrupt that is triggered while masked will fire once the
733 // interrupt is unmasked.
734 #[test]
level_trigger_unmask_test()735 fn level_trigger_unmask_test() {
736 let (mut ioapic, irq) = set_up(TriggerMode::Level);
737
738 set_mask(&mut ioapic, irq, true);
739 ioapic.service_irq(irq, true);
740
741 // TODO(mutexlox): expect an interrupt after this.
742 set_mask(&mut ioapic, irq, false);
743 }
744
745 // Verify that multiple asserts before a deassert are ignored even if there's an EOI between
746 // them.
747 #[test]
end_of_interrupt_edge_triggered_irq()748 fn end_of_interrupt_edge_triggered_irq() {
749 let (mut ioapic, irq) = set_up(TriggerMode::Edge);
750
751 // TODO(mutexlox): Expect 1 interrupt.
752 ioapic.service_irq(irq, true);
753 ioapic.end_of_interrupt(DEFAULT_DESTINATION_ID);
754 // Repeated asserts before a de-assert should be ignored.
755 ioapic.service_irq(irq, true);
756 ioapic.service_irq(irq, false);
757 }
758
759 // Send multiple edge-triggered interrupts in a row.
760 #[test]
service_multiple_edge_irqs()761 fn service_multiple_edge_irqs() {
762 let (mut ioapic, irq) = set_up(TriggerMode::Edge);
763
764 ioapic.service_irq(irq, true);
765 // TODO(mutexlox): Verify that an interrupt occurs here.
766 ioapic.service_irq(irq, false);
767
768 ioapic.service_irq(irq, true);
769 // TODO(mutexlox): Verify that an interrupt occurs here.
770 ioapic.service_irq(irq, false);
771 }
772
773 // Test an interrupt line with negative polarity.
774 #[test]
service_negative_polarity_irq()775 fn service_negative_polarity_irq() {
776 let (mut ioapic, irq) = set_up(TriggerMode::Level);
777
778 let mut entry = read_entry(&mut ioapic, irq);
779 entry.set_polarity(1);
780 write_entry(&mut ioapic, irq, entry);
781
782 // TODO(mutexlox): Expect an interrupt to fire.
783 ioapic.service_irq(irq, false);
784 }
785
786 // Ensure that remote IRR can't be edited via mmio.
787 #[test]
remote_irr_read_only()788 fn remote_irr_read_only() {
789 let (mut ioapic, irq) = set_up(TriggerMode::Level);
790
791 ioapic.redirect_table[irq].set_remote_irr(true);
792
793 let mut entry = read_entry(&mut ioapic, irq);
794 entry.set_remote_irr(false);
795 write_entry(&mut ioapic, irq, entry);
796
797 assert_eq!(read_entry(&mut ioapic, irq).get_remote_irr(), true);
798 }
799
800 #[test]
delivery_status_read_only()801 fn delivery_status_read_only() {
802 let (mut ioapic, irq) = set_up(TriggerMode::Level);
803
804 ioapic.redirect_table[irq].set_delivery_status(DeliveryStatus::Pending);
805
806 let mut entry = read_entry(&mut ioapic, irq);
807 entry.set_delivery_status(DeliveryStatus::Idle);
808 write_entry(&mut ioapic, irq, entry);
809
810 assert_eq!(
811 read_entry(&mut ioapic, irq).get_delivery_status(),
812 DeliveryStatus::Pending
813 );
814 }
815
816 #[test]
level_to_edge_transition_clears_remote_irr()817 fn level_to_edge_transition_clears_remote_irr() {
818 let (mut ioapic, irq) = set_up(TriggerMode::Level);
819
820 ioapic.redirect_table[irq].set_remote_irr(true);
821
822 let mut entry = read_entry(&mut ioapic, irq);
823 entry.set_trigger_mode(TriggerMode::Edge);
824 write_entry(&mut ioapic, irq, entry);
825
826 assert_eq!(read_entry(&mut ioapic, irq).get_remote_irr(), false);
827 }
828
829 #[test]
masking_preserves_remote_irr()830 fn masking_preserves_remote_irr() {
831 let (mut ioapic, irq) = set_up(TriggerMode::Level);
832
833 ioapic.redirect_table[irq].set_remote_irr(true);
834
835 set_mask(&mut ioapic, irq, true);
836 set_mask(&mut ioapic, irq, false);
837
838 assert_eq!(read_entry(&mut ioapic, irq).get_remote_irr(), true);
839 }
840
841 // Test reconfiguration racing with EOIs.
842 #[test]
reconfiguration_race()843 fn reconfiguration_race() {
844 let (mut ioapic, irq) = set_up(TriggerMode::Level);
845
846 // Fire one level-triggered interrupt.
847 // TODO(mutexlox): Check that it fires.
848 ioapic.service_irq(irq, true);
849
850 // Read the redirection table entry before the EOI...
851 let mut entry = read_entry(&mut ioapic, irq);
852 entry.set_trigger_mode(TriggerMode::Edge);
853
854 ioapic.service_irq(irq, false);
855 ioapic.end_of_interrupt(DEFAULT_DESTINATION_ID);
856
857 // ... and write back that (modified) value.
858 write_entry(&mut ioapic, irq, entry);
859
860 // Fire one *edge* triggered interrupt
861 // TODO(mutexlox): Assert that the interrupt fires once.
862 ioapic.service_irq(irq, true);
863 ioapic.service_irq(irq, false);
864 }
865
866 // Ensure that swapping to edge triggered and back clears the remote irr bit.
867 #[test]
implicit_eoi()868 fn implicit_eoi() {
869 let (mut ioapic, irq) = set_up(TriggerMode::Level);
870
871 // Fire one level-triggered interrupt.
872 ioapic.service_irq(irq, true);
873 // TODO(mutexlox): Verify that one interrupt was fired.
874 ioapic.service_irq(irq, false);
875
876 // Do an implicit EOI by cycling between edge and level triggered.
877 let mut entry = read_entry(&mut ioapic, irq);
878 entry.set_trigger_mode(TriggerMode::Edge);
879 write_entry(&mut ioapic, irq, entry);
880 entry.set_trigger_mode(TriggerMode::Level);
881 write_entry(&mut ioapic, irq, entry);
882
883 // Fire one level-triggered interrupt.
884 ioapic.service_irq(irq, true);
885 // TODO(mutexlox): Verify that one interrupt fires.
886 ioapic.service_irq(irq, false);
887 }
888
889 #[test]
set_redirection_entry_by_bits()890 fn set_redirection_entry_by_bits() {
891 let mut entry = IoapicRedirectionTableEntry::new();
892 // destination_mode
893 // polarity |
894 // trigger_mode | |
895 // | | |
896 // 0011 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1001 0110 0101 1111
897 // |_______| |______________________________________________|| | | |_| |_______|
898 // dest_id reserved | | | | vector
899 // interrupt_mask | | |
900 // remote_irr | |
901 // delivery_status |
902 // delivery_mode
903 entry.set(0, 64, 0x3a0000000000965f);
904 assert_eq!(entry.get_vector(), 0x5f);
905 assert_eq!(entry.get_delivery_mode(), DeliveryMode::Startup);
906 assert_eq!(entry.get_dest_mode(), DestinationMode::Physical);
907 assert_eq!(entry.get_delivery_status(), DeliveryStatus::Pending);
908 assert_eq!(entry.get_polarity(), 0);
909 assert_eq!(entry.get_remote_irr(), false);
910 assert_eq!(entry.get_trigger_mode(), TriggerMode::Level);
911 assert_eq!(entry.get_interrupt_mask(), false);
912 assert_eq!(entry.get_reserved(), 0);
913 assert_eq!(entry.get_dest_id(), 0x3a);
914
915 let (mut ioapic, irq) = set_up(TriggerMode::Edge);
916 write_entry(&mut ioapic, irq, entry);
917 assert_eq!(
918 read_entry(&mut ioapic, irq).get_trigger_mode(),
919 TriggerMode::Level
920 );
921
922 // TODO(mutexlox): Verify that this actually fires an interrupt.
923 ioapic.service_irq(irq, true);
924 }
925 }
926