1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Ben Widawsky <ben@bwidawsk.net>
26 *
27 */
28
29 #include <unistd.h>
30 #include <fcntl.h>
31 #include <stdio.h>
32 #include <stdarg.h>
33 #include <stdlib.h>
34 #include <stdint.h>
35 #include <stdbool.h>
36 #include <string.h>
37 #include <errno.h>
38 #include <err.h>
39 #include <assert.h>
40 #include <sys/ioctl.h>
41 #include <sys/stat.h>
42 #include <sys/mman.h>
43
44 #include "intel_io.h"
45 #include "igt_core.h"
46 #include "igt_gt.h"
47 #include "intel_chipset.h"
48
49 /**
50 * SECTION:intel_io
51 * @short_description: Register access and sideband I/O library
52 * @title: I/O
53 * @include: igt.h
54 * @section_id: igt-gpu-tools-IO
55 *
56 * This library provides register I/O helpers in both a basic version and a more
57 * fancy version which also handles forcewake and can optionally check registers
58 * against a white-list. All register function are compatible. Hence the same
59 * code can be used to decode registers with either of them, or also from a dump
60 * file using intel_mmio_use_dump_file().
61 *
62 * Furthermore this library also provides helper functions for accessing the
63 * various sideband interfaces found on Valleyview/Baytrail based platforms.
64 */
65
66 #define FAKEKEY 0x2468ace0
67
68 /**
69 * igt_global_mmio:
70 *
71 * Pointer to the register range, initialized using intel_register_access_init()
72 * or intel_mmio_use_dump_file(). It is not recommended to use this directly.
73 */
74 void *igt_global_mmio;
75
76 static struct _mmio_data {
77 int inited;
78 bool safe;
79 uint32_t i915_devid;
80 struct intel_register_map map;
81 int key;
82 } mmio_data;
83
84 /**
85 * intel_mmio_use_dump_file:
86 * @file: name of the register dump file to open
87 *
88 * Sets up #igt_global_mmio to point at the data contained in @file. This allows
89 * the same code to get reused for dumping and decoding from running hardware as
90 * from register dumps.
91 */
92 void
intel_mmio_use_dump_file(char * file)93 intel_mmio_use_dump_file(char *file)
94 {
95 int fd;
96 struct stat st;
97
98 fd = open(file, O_RDWR);
99 igt_fail_on_f(fd == -1,
100 "Couldn't open %s\n", file);
101
102 fstat(fd, &st);
103 igt_global_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
104 igt_fail_on_f(igt_global_mmio == MAP_FAILED,
105 "Couldn't mmap %s\n", file);
106 close(fd);
107 }
108
109 /**
110 * intel_mmio_use_pci_bar:
111 * @pci_dev: intel gracphis pci device
112 *
113 * Sets up #igt_global_mmio to point at the mmio bar.
114 *
115 * @pci_dev can be obtained from intel_get_pci_device().
116 */
117 void
intel_mmio_use_pci_bar(struct pci_device * pci_dev)118 intel_mmio_use_pci_bar(struct pci_device *pci_dev)
119 {
120 uint32_t devid, gen;
121 int mmio_bar, mmio_size;
122 int error;
123
124 devid = pci_dev->device_id;
125 if (IS_GEN2(devid))
126 mmio_bar = 1;
127 else
128 mmio_bar = 0;
129
130 gen = intel_gen(devid);
131 if (gen < 3)
132 mmio_size = 512*1024;
133 else if (gen < 5)
134 mmio_size = 512*1024;
135 else
136 mmio_size = 2*1024*1024;
137
138 error = pci_device_map_range (pci_dev,
139 pci_dev->regions[mmio_bar].base_addr,
140 mmio_size,
141 PCI_DEV_MAP_FLAG_WRITABLE,
142 &igt_global_mmio);
143
144 igt_fail_on_f(error != 0,
145 "Couldn't map MMIO region\n");
146 }
147
148 static void
release_forcewake_lock(int fd)149 release_forcewake_lock(int fd)
150 {
151 close(fd);
152 }
153
154 /**
155 * intel_register_access_init:
156 * @pci_dev: intel graphics pci device
157 * @safe: use safe register access tables
158 *
159 * This initializes the new register access library, which supports forcewake
160 * handling and also allows register access to be checked with an explicit
161 * whitelist.
162 *
163 * It also initializes #igt_global_mmio like intel_mmio_use_pci_bar().
164 *
165 * @pci_dev can be obtained from intel_get_pci_device().
166 */
167 int
intel_register_access_init(struct pci_device * pci_dev,int safe,int fd)168 intel_register_access_init(struct pci_device *pci_dev, int safe, int fd)
169 {
170 int ret;
171
172 /* after old API is deprecated, remove this */
173 if (igt_global_mmio == NULL)
174 intel_mmio_use_pci_bar(pci_dev);
175
176 igt_assert(igt_global_mmio != NULL);
177
178 if (mmio_data.inited)
179 return -1;
180
181 mmio_data.safe = (safe != 0 &&
182 intel_gen(pci_dev->device_id) >= 4) ? true : false;
183 mmio_data.i915_devid = pci_dev->device_id;
184 if (mmio_data.safe)
185 mmio_data.map = intel_get_register_map(mmio_data.i915_devid);
186
187 /* Find where the forcewake lock is. Forcewake doesn't exist
188 * gen < 6, but the debugfs should do the right things for us.
189 */
190 ret = igt_open_forcewake_handle(fd);
191 if (ret == -1)
192 mmio_data.key = FAKEKEY;
193 else
194 mmio_data.key = ret;
195
196 mmio_data.inited++;
197 return 0;
198 }
199
200 static int
intel_register_access_needs_wake(void)201 intel_register_access_needs_wake(void)
202 {
203 return mmio_data.key != FAKEKEY;
204 }
205
206 /**
207 * intel_register_access_needs_fakewake:
208 *
209 * Returns:
210 * Non-zero when forcewake initialization failed.
211 */
intel_register_access_needs_fakewake(void)212 int intel_register_access_needs_fakewake(void)
213 {
214 return mmio_data.key == FAKEKEY;
215 }
216
217 /**
218 * intel_register_access_fini:
219 *
220 * Clean up the register access helper initialized with
221 * intel_register_access_init().
222 */
223 void
intel_register_access_fini(void)224 intel_register_access_fini(void)
225 {
226 if (mmio_data.key && intel_register_access_needs_wake())
227 release_forcewake_lock(mmio_data.key);
228 mmio_data.inited--;
229 }
230
231 /**
232 * intel_register_read:
233 * @reg: register offset
234 *
235 * 32-bit read of the register at @offset. This function only works when the new
236 * register access helper is initialized with intel_register_access_init().
237 *
238 * Compared to INREG() it can do optional checking with the register access
239 * white lists.
240 *
241 * Returns:
242 * The value read from the register.
243 */
244 uint32_t
intel_register_read(uint32_t reg)245 intel_register_read(uint32_t reg)
246 {
247 struct intel_register_range *range;
248 uint32_t ret;
249
250 igt_assert(mmio_data.inited);
251
252 if (intel_gen(mmio_data.i915_devid) >= 6)
253 igt_assert(mmio_data.key != -1);
254
255 if (!mmio_data.safe)
256 goto read_out;
257
258 range = intel_get_register_range(mmio_data.map,
259 reg,
260 INTEL_RANGE_READ);
261
262 if(!range) {
263 igt_warn("Register read blocked for safety ""(*0x%08x)\n", reg);
264 ret = 0xffffffff;
265 goto out;
266 }
267
268 read_out:
269 ret = *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg);
270 out:
271 return ret;
272 }
273
274 /**
275 * intel_register_write:
276 * @reg: register offset
277 * @val: value to write
278 *
279 * 32-bit write to the register at @offset. This function only works when the new
280 * register access helper is initialized with intel_register_access_init().
281 *
282 * Compared to OUTREG() it can do optional checking with the register access
283 * white lists.
284 */
285 void
intel_register_write(uint32_t reg,uint32_t val)286 intel_register_write(uint32_t reg, uint32_t val)
287 {
288 struct intel_register_range *range;
289
290 igt_assert(mmio_data.inited);
291
292 if (intel_gen(mmio_data.i915_devid) >= 6)
293 igt_assert(mmio_data.key != -1);
294
295 if (!mmio_data.safe)
296 goto write_out;
297
298 range = intel_get_register_range(mmio_data.map,
299 reg,
300 INTEL_RANGE_WRITE);
301
302 igt_warn_on_f(!range,
303 "Register write blocked for safety ""(*0x%08x = 0x%x)\n", reg, val);
304
305 write_out:
306 *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val;
307 }
308
309
310 /**
311 * INREG:
312 * @reg: register offset
313 *
314 * 32-bit read of the register at offset @reg. This function only works when the
315 * new register access helper is initialized with intel_register_access_init().
316 *
317 * This function directly accesses the #igt_global_mmio without safety checks.
318 *
319 * Returns:
320 * The value read from the register.
321 */
INREG(uint32_t reg)322 uint32_t INREG(uint32_t reg)
323 {
324 return *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg);
325 }
326
327 /**
328 * INREG16:
329 * @reg: register offset
330 *
331 * 16-bit read of the register at offset @reg. This function only works when the
332 * new register access helper is initialized with intel_register_access_init().
333 *
334 * This function directly accesses the #igt_global_mmio without safety checks.
335 *
336 * Returns:
337 * The value read from the register.
338 */
INREG16(uint32_t reg)339 uint16_t INREG16(uint32_t reg)
340 {
341 return *(volatile uint16_t *)((volatile char *)igt_global_mmio + reg);
342 }
343
344 /**
345 * INREG8:
346 * @reg: register offset
347 *
348 * 8-bit read of the register at offset @reg. This function only works when the
349 * new register access helper is initialized with intel_register_access_init().
350 *
351 * This function directly accesses the #igt_global_mmio without safety checks.
352 *
353 * Returns:
354 * The value read from the register.
355 */
INREG8(uint32_t reg)356 uint8_t INREG8(uint32_t reg)
357 {
358 return *((volatile uint8_t *)igt_global_mmio + reg);
359 }
360
361 /**
362 * OUTREG:
363 * @reg: register offset
364 * @val: value to write
365 *
366 * 32-bit write of @val to the register at offset @reg. This function only works
367 * when the new register access helper is initialized with
368 * intel_register_access_init().
369 *
370 * This function directly accesses the #igt_global_mmio without safety checks.
371 */
OUTREG(uint32_t reg,uint32_t val)372 void OUTREG(uint32_t reg, uint32_t val)
373 {
374 *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val;
375 }
376
377 /**
378 * OUTREG16:
379 * @reg: register offset
380 * @val: value to write
381 *
382 * 16-bit write of @val to the register at offset @reg. This function only works
383 * when the new register access helper is initialized with
384 * intel_register_access_init().
385 *
386 * This function directly accesses the #igt_global_mmio without safety checks.
387 */
OUTREG16(uint32_t reg,uint16_t val)388 void OUTREG16(uint32_t reg, uint16_t val)
389 {
390 *(volatile uint16_t *)((volatile char *)igt_global_mmio + reg) = val;
391 }
392
393 /**
394 * OUTREG8:
395 * @reg: register offset
396 * @val: value to write
397 *
398 * 8-bit write of @val to the register at offset @reg. This function only works
399 * when the new register access helper is initialized with
400 * intel_register_access_init().
401 *
402 * This function directly accesses the #igt_global_mmio without safety checks.
403 */
OUTREG8(uint32_t reg,uint8_t val)404 void OUTREG8(uint32_t reg, uint8_t val)
405 {
406 *((volatile uint8_t *)igt_global_mmio + reg) = val;
407 }
408