1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jeff McGee <jeff.mcgee@intel.com>
25 */
26
27 #include <intel_bufmgr.h>
28 #include <i915_drm.h>
29 #include "intel_reg.h"
30 #include "drmtest.h"
31 #include "intel_batchbuffer.h"
32 #include "gen8_media.h"
33 #include "media_spin.h"
34 #include "gpu_cmds.h"
35
36 static const uint32_t spin_kernel[][4] = {
37 { 0x00600001, 0x20800208, 0x008d0000, 0x00000000 }, /* mov (8)r4.0<1>:ud r0.0<8;8;1>:ud */
38 { 0x00200001, 0x20800208, 0x00450040, 0x00000000 }, /* mov (2)r4.0<1>.ud r2.0<2;2;1>:ud */
39 { 0x00000001, 0x20880608, 0x00000000, 0x00000003 }, /* mov (1)r4.8<1>:ud 0x3 */
40 { 0x00000001, 0x20a00608, 0x00000000, 0x00000000 }, /* mov (1)r5.0<1>:ud 0 */
41 { 0x00000040, 0x20a00208, 0x060000a0, 0x00000001 }, /* add (1)r5.0<1>:ud r5.0<0;1;0>:ud 1 */
42 { 0x01000010, 0x20000200, 0x02000020, 0x000000a0 }, /* cmp.e.f0.0 (1)null<1> r1<0;1;0> r5<0;1;0> */
43 { 0x00110027, 0x00000000, 0x00000000, 0xffffffe0 }, /* ~f0.0 while (1) -32 */
44 { 0x0c800031, 0x20000a00, 0x0e000080, 0x040a8000 }, /* send.dcdp1 (16)null<1> r4.0<0;1;0> 0x040a8000 */
45 { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, /* mov (8)r112<1>:ud r0.0<8;8;1>:ud */
46 { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, /* send.ts (16)null<1> r112<0;1;0>:d 0x82000010 */
47 };
48
49 /*
50 * This sets up the media pipeline,
51 *
52 * +---------------+ <---- 4096
53 * | ^ |
54 * | | |
55 * | various |
56 * | state |
57 * | | |
58 * |_______|_______| <---- 2048 + ?
59 * | ^ |
60 * | | |
61 * | batch |
62 * | commands |
63 * | | |
64 * | | |
65 * +---------------+ <---- 0 + ?
66 *
67 */
68
69 #define BATCH_STATE_SPLIT 2048
70 /* VFE STATE params */
71 #define THREADS 0
72 #define MEDIA_URB_ENTRIES 2
73 #define MEDIA_URB_SIZE 2
74 #define MEDIA_CURBE_SIZE 2
75
76 /* Offsets needed in gen_emit_media_object. In media_spin library this
77 * values do not matter.
78 */
79 #define xoffset 0
80 #define yoffset 0
81
82 void
gen8_media_spinfunc(struct intel_batchbuffer * batch,const struct igt_buf * dst,uint32_t spins)83 gen8_media_spinfunc(struct intel_batchbuffer *batch,
84 const struct igt_buf *dst, uint32_t spins)
85 {
86 uint32_t curbe_buffer, interface_descriptor;
87 uint32_t batch_end;
88
89 intel_batchbuffer_flush_with_context(batch, NULL);
90
91 /* setup states */
92 batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
93
94 curbe_buffer = gen8_spin_curbe_buffer_data(batch, spins);
95 interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
96 spin_kernel, sizeof(spin_kernel));
97 igt_assert(batch->ptr < &batch->buffer[4095]);
98
99 /* media pipeline */
100 batch->ptr = batch->buffer;
101 OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
102 gen8_emit_state_base_address(batch);
103
104 gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES,
105 MEDIA_URB_SIZE, MEDIA_CURBE_SIZE);
106
107 gen7_emit_curbe_load(batch, curbe_buffer);
108
109 gen7_emit_interface_descriptor_load(batch, interface_descriptor);
110
111 gen_emit_media_object(batch, xoffset, yoffset);
112
113 OUT_BATCH(MI_BATCH_BUFFER_END);
114
115 batch_end = intel_batchbuffer_align(batch, 8);
116 igt_assert(batch_end < BATCH_STATE_SPLIT);
117
118 gen7_render_flush(batch, batch_end);
119 intel_batchbuffer_reset(batch);
120 }
121
122 void
gen9_media_spinfunc(struct intel_batchbuffer * batch,const struct igt_buf * dst,uint32_t spins)123 gen9_media_spinfunc(struct intel_batchbuffer *batch,
124 const struct igt_buf *dst, uint32_t spins)
125 {
126 uint32_t curbe_buffer, interface_descriptor;
127 uint32_t batch_end;
128
129 intel_batchbuffer_flush_with_context(batch, NULL);
130
131 /* setup states */
132 batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
133
134 curbe_buffer = gen8_spin_curbe_buffer_data(batch, spins);
135 interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
136 spin_kernel, sizeof(spin_kernel));
137 igt_assert(batch->ptr < &batch->buffer[4095]);
138
139 /* media pipeline */
140 batch->ptr = batch->buffer;
141 OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
142 GEN9_FORCE_MEDIA_AWAKE_ENABLE |
143 GEN9_SAMPLER_DOP_GATE_DISABLE |
144 GEN9_PIPELINE_SELECTION_MASK |
145 GEN9_SAMPLER_DOP_GATE_MASK |
146 GEN9_FORCE_MEDIA_AWAKE_MASK);
147 gen9_emit_state_base_address(batch);
148
149 gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES,
150 MEDIA_URB_SIZE, MEDIA_CURBE_SIZE);
151
152 gen7_emit_curbe_load(batch, curbe_buffer);
153
154 gen7_emit_interface_descriptor_load(batch, interface_descriptor);
155
156 gen_emit_media_object(batch, xoffset, yoffset);
157
158 OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
159 GEN9_FORCE_MEDIA_AWAKE_DISABLE |
160 GEN9_SAMPLER_DOP_GATE_ENABLE |
161 GEN9_PIPELINE_SELECTION_MASK |
162 GEN9_SAMPLER_DOP_GATE_MASK |
163 GEN9_FORCE_MEDIA_AWAKE_MASK);
164
165 OUT_BATCH(MI_BATCH_BUFFER_END);
166
167 batch_end = intel_batchbuffer_align(batch, 8);
168 igt_assert(batch_end < BATCH_STATE_SPLIT);
169
170 gen7_render_flush(batch, batch_end);
171 intel_batchbuffer_reset(batch);
172 }
173