1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include "igt.h"
30 #include <stdlib.h>
31 #include <stdio.h>
32 #include <string.h>
33 #include <fcntl.h>
34 #include <inttypes.h>
35 #include <errno.h>
36 #include <sys/stat.h>
37 #include <sys/time.h>
38
39 #include <drm.h>
40
41 #include "intel_bufmgr.h"
42
43 IGT_TEST_DESCRIPTION("Test snoop consistency when touching partial"
44 " cachelines.");
45
46 /*
47 * Testcase: snoop consistency when touching partial cachelines
48 *
49 */
50
51 static drm_intel_bufmgr *bufmgr;
52 struct intel_batchbuffer *batch;
53
54 drm_intel_bo *scratch_bo;
55 drm_intel_bo *staging_bo;
56 #define BO_SIZE (4*4096)
57 uint32_t devid;
58 int fd;
59
60 static void
copy_bo(drm_intel_bo * src,drm_intel_bo * dst)61 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
62 {
63 BLIT_COPY_BATCH_START(0);
64 OUT_BATCH((3 << 24) | /* 32 bits */
65 (0xcc << 16) | /* copy ROP */
66 4096);
67 OUT_BATCH(0 << 16 | 0);
68 OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
69 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
70 OUT_BATCH(0 << 16 | 0);
71 OUT_BATCH(4096);
72 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
73 ADVANCE_BATCH();
74
75 intel_batchbuffer_flush(batch);
76 }
77
78 static void
blt_bo_fill(drm_intel_bo * tmp_bo,drm_intel_bo * bo,uint8_t val)79 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
80 {
81 uint8_t *gtt_ptr;
82 int i;
83
84 do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
85 gtt_ptr = tmp_bo->virtual;
86
87 for (i = 0; i < BO_SIZE; i++)
88 gtt_ptr[i] = val;
89
90 drm_intel_gem_bo_unmap_gtt(tmp_bo);
91
92 igt_drop_caches_set(fd, DROP_BOUND);
93
94 copy_bo(tmp_bo, bo);
95 }
96
97 #define MAX_BLT_SIZE 128
98 #define ROUNDS 1000
99 #define TEST_READ 0x1
100 #define TEST_WRITE 0x2
101 #define TEST_BOTH (TEST_READ | TEST_WRITE)
102 igt_main
103 {
104 unsigned flags = TEST_BOTH;
105 int i, j;
106 uint8_t *cpu_ptr;
107 uint8_t *gtt_ptr;
108
109 igt_skip_on_simulation();
110
111 igt_fixture {
112 srandom(0xdeadbeef);
113
114 fd = drm_open_driver(DRIVER_INTEL);
115
116 igt_require_gem(fd);
117 gem_require_caching(fd);
118
119 devid = intel_get_drm_devid(fd);
120 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
121 flags &= ~TEST_READ;
122 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
123 /* chipset is completely fubar */
124 igt_info("coherency broken on i965g/gm\n");
125 flags = 0;
126 }
127
128 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
129 batch = intel_batchbuffer_alloc(bufmgr, devid);
130
131 /* overallocate the buffers we're actually using because */
132 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
133 gem_set_caching(fd, scratch_bo->handle, 1);
134
135 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
136 }
137
138 igt_subtest("reads") {
139 igt_require(flags & TEST_READ);
140
141 igt_info("checking partial reads\n");
142
143 for (i = 0; i < ROUNDS; i++) {
144 uint8_t val0 = i;
145 int start, len;
146
147 blt_bo_fill(staging_bo, scratch_bo, i);
148
149 start = random() % BO_SIZE;
150 len = random() % (BO_SIZE-start) + 1;
151
152 drm_intel_bo_map(scratch_bo, false);
153 cpu_ptr = scratch_bo->virtual;
154 for (j = 0; j < len; j++) {
155 igt_assert_f(cpu_ptr[j] == val0,
156 "mismatch at %i, got: %i, expected: %i\n",
157 j, cpu_ptr[j], val0);
158 }
159 drm_intel_bo_unmap(scratch_bo);
160
161 igt_progress("partial reads test: ", i, ROUNDS);
162 }
163 }
164
165 igt_subtest("writes") {
166 igt_require(flags & TEST_WRITE);
167
168 igt_info("checking partial writes\n");
169
170 for (i = 0; i < ROUNDS; i++) {
171 uint8_t val0 = i, val1;
172 int start, len;
173
174 blt_bo_fill(staging_bo, scratch_bo, val0);
175
176 start = random() % BO_SIZE;
177 len = random() % (BO_SIZE-start) + 1;
178
179 val1 = val0 + 63;
180 drm_intel_bo_map(scratch_bo, true);
181 cpu_ptr = scratch_bo->virtual;
182 memset(cpu_ptr + start, val1, len);
183 drm_intel_bo_unmap(scratch_bo);
184
185 copy_bo(scratch_bo, staging_bo);
186 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
187 gtt_ptr = staging_bo->virtual;
188
189 for (j = 0; j < start; j++) {
190 igt_assert_f(gtt_ptr[j] == val0,
191 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
192 j, start, len, gtt_ptr[j], val0);
193 }
194 for (; j < start + len; j++) {
195 igt_assert_f(gtt_ptr[j] == val1,
196 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
197 j, start, len, gtt_ptr[j], val1);
198 }
199 for (; j < BO_SIZE; j++) {
200 igt_assert_f(gtt_ptr[j] == val0,
201 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
202 j, start, len, gtt_ptr[j], val0);
203 }
204 drm_intel_gem_bo_unmap_gtt(staging_bo);
205
206 igt_progress("partial writes test: ", i, ROUNDS);
207 }
208 }
209
210 igt_subtest("read-writes") {
211 igt_require((flags & TEST_BOTH) == TEST_BOTH);
212
213 igt_info("checking partial writes after partial reads\n");
214
215 for (i = 0; i < ROUNDS; i++) {
216 uint8_t val0 = i, val1, val2;
217 int start, len;
218
219 blt_bo_fill(staging_bo, scratch_bo, val0);
220
221 /* partial read */
222 start = random() % BO_SIZE;
223 len = random() % (BO_SIZE-start) + 1;
224
225 do_or_die(drm_intel_bo_map(scratch_bo, false));
226 cpu_ptr = scratch_bo->virtual;
227 for (j = 0; j < len; j++) {
228 igt_assert_f(cpu_ptr[j] == val0,
229 "mismatch in read at %i, got: %i, expected: %i\n",
230 j, cpu_ptr[j], val0);
231 }
232 drm_intel_bo_unmap(scratch_bo);
233
234 /* Change contents through gtt to make the pread cachelines
235 * stale. */
236 val1 = i + 17;
237 blt_bo_fill(staging_bo, scratch_bo, val1);
238
239 /* partial write */
240 start = random() % BO_SIZE;
241 len = random() % (BO_SIZE-start) + 1;
242
243 val2 = i + 63;
244 do_or_die(drm_intel_bo_map(scratch_bo, false));
245 cpu_ptr = scratch_bo->virtual;
246 memset(cpu_ptr + start, val2, len);
247
248 copy_bo(scratch_bo, staging_bo);
249 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
250 gtt_ptr = staging_bo->virtual;
251
252 for (j = 0; j < start; j++) {
253 igt_assert_f(gtt_ptr[j] == val1,
254 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
255 j, start, len, gtt_ptr[j], val1);
256 }
257 for (; j < start + len; j++) {
258 igt_assert_f(gtt_ptr[j] == val2,
259 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
260 j, start, len, gtt_ptr[j], val2);
261 }
262 for (; j < BO_SIZE; j++) {
263 igt_assert_f(gtt_ptr[j] == val1,
264 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
265 j, start, len, gtt_ptr[j], val1);
266 }
267 drm_intel_gem_bo_unmap_gtt(staging_bo);
268 drm_intel_bo_unmap(scratch_bo);
269
270 igt_progress("partial read/writes test: ", i, ROUNDS);
271 }
272 }
273
274 igt_fixture {
275 drm_intel_bufmgr_destroy(bufmgr);
276
277 close(fd);
278 }
279 }
280