1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
25 *
26 */
27
28 #include "igt.h"
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <string.h>
32 #include <fcntl.h>
33 #include <inttypes.h>
34 #include <errno.h>
35 #include <sys/stat.h>
36 #include <sys/time.h>
37 #include "drm.h"
38 #include "intel_bufmgr.h"
39 #include "i830_reg.h"
40
41 static drm_intel_bufmgr *bufmgr;
42 struct intel_batchbuffer *batch;
43 static drm_intel_bo *target_buffer, *blt_bo;
44
45 /*
46 * Testcase: Basic check for missed irqs on blt
47 *
48 * Execs one large and then immediately a tiny batch on the blt ring. Then waits
49 * on the second batch. This hopefully catches races in our irq acknowledgement.
50 */
51
52 IGT_TEST_DESCRIPTION("Basic check for missed IRQs on blt ring.");
53
54
55 #define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
56 #define MI_DO_COMPARE (1<<21)
57 static void
dummy_reloc_loop(void)58 dummy_reloc_loop(void)
59 {
60 int i;
61
62 for (i = 0; i < 0x800; i++) {
63 BLIT_COPY_BATCH_START(0);
64 OUT_BATCH((3 << 24) | /* 32 bits */
65 (0xcc << 16) | /* copy ROP */
66 4*4096);
67 OUT_BATCH(2048 << 16 | 0);
68 OUT_BATCH((4096) << 16 | (2048));
69 OUT_RELOC_FENCED(blt_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
70 OUT_BATCH(0 << 16 | 0);
71 OUT_BATCH(4*4096);
72 OUT_RELOC_FENCED(blt_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
73 ADVANCE_BATCH();
74 intel_batchbuffer_flush(batch);
75
76 BEGIN_BATCH(4, 1);
77 OUT_BATCH(MI_FLUSH_DW | 1);
78 OUT_BATCH(0); /* reserved */
79 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
80 I915_GEM_DOMAIN_RENDER, 0);
81 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
82 ADVANCE_BATCH();
83 intel_batchbuffer_flush(batch);
84
85 drm_intel_bo_map(target_buffer, 0);
86 // map to force completion
87 drm_intel_bo_unmap(target_buffer);
88 }
89 }
90
91 igt_simple_main
92 {
93 int fd;
94 int devid;
95
96 igt_skip_on_simulation();
97
98 fd = drm_open_driver(DRIVER_INTEL);
99 igt_require_gem(fd);
100 devid = intel_get_drm_devid(fd);
101 igt_require_f(HAS_BLT_RING(devid),
102 "not (yet) implemented for pre-snb\n");
103
104 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
105 igt_assert(bufmgr);
106 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
107
108 batch = intel_batchbuffer_alloc(bufmgr, devid);
109 igt_assert(batch);
110
111 target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
112 igt_assert(target_buffer);
113
114 blt_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4*4096*4096, 4096);
115 igt_assert(blt_bo);
116
117 dummy_reloc_loop();
118
119 drm_intel_bo_unreference(target_buffer);
120 intel_batchbuffer_free(batch);
121 drm_intel_bufmgr_destroy(bufmgr);
122
123 close(fd);
124 }
125