1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
25 *
26 */
27
28 #include "igt.h"
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <string.h>
32 #include <fcntl.h>
33 #include <inttypes.h>
34 #include <errno.h>
35 #include <sys/stat.h>
36 #include <sys/time.h>
37 #include "drm.h"
38 #include "intel_bufmgr.h"
39
40 /* Testcase: Test whether the kernel rejects relocations with non-gpu domains
41 *
42 * If it does not, it'll oops somewhen later on because we don't expect that.
43 */
44
45 IGT_TEST_DESCRIPTION("Test whether the kernel rejects relocations with non-gpu"
46 " domains.");
47
48 static drm_intel_bufmgr *bufmgr;
49 struct intel_batchbuffer *batch;
50
51 #define BAD_GTT_DEST ((512*1024*1024)) /* past end of aperture */
52
53 static int
run_batch(void)54 run_batch(void)
55 {
56 unsigned int used = batch->ptr - batch->buffer;
57 int ret;
58
59 if (used == 0)
60 return 0;
61
62 /* Round batchbuffer usage to 2 DWORDs. */
63 if ((used & 4) == 0) {
64 *(uint32_t *) (batch->ptr) = 0; /* noop */
65 batch->ptr += 4;
66 }
67
68 /* Mark the end of the buffer. */
69 *(uint32_t *)(batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
70 batch->ptr += 4;
71 used = batch->ptr - batch->buffer;
72
73 ret = drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer);
74 igt_assert_eq(ret, 0);
75
76 batch->ptr = NULL;
77
78 ret = drm_intel_bo_mrb_exec(batch->bo, used, NULL, 0, 0, 0);
79
80 intel_batchbuffer_reset(batch);
81
82 return ret;
83 }
84
85 #define I915_GEM_GPU_DOMAINS \
86 (I915_GEM_DOMAIN_RENDER | \
87 I915_GEM_DOMAIN_SAMPLER | \
88 I915_GEM_DOMAIN_COMMAND | \
89 I915_GEM_DOMAIN_INSTRUCTION | \
90 I915_GEM_DOMAIN_VERTEX)
91
multi_write_domain(int fd)92 static void multi_write_domain(int fd)
93 {
94 struct drm_i915_gem_execbuffer2 execbuf;
95 struct drm_i915_gem_exec_object2 exec[2];
96 struct drm_i915_gem_relocation_entry reloc[1];
97 uint32_t handle, handle_target;
98
99 handle = gem_create(fd, 4096);
100 handle_target = gem_create(fd, 4096);
101
102 exec[0].handle = handle_target;
103 exec[0].relocation_count = 0;
104 exec[0].relocs_ptr = 0;
105 exec[0].alignment = 0;
106 exec[0].offset = 0;
107 exec[0].flags = 0;
108 exec[0].rsvd1 = 0;
109 exec[0].rsvd2 = 0;
110
111 exec[1].handle = handle;
112 exec[1].relocation_count = 1;
113 exec[1].relocs_ptr = to_user_pointer(reloc);
114 exec[1].alignment = 0;
115 exec[1].offset = 0;
116 exec[1].flags = 0;
117 exec[1].rsvd1 = 0;
118 exec[1].rsvd2 = 0;
119
120 reloc[0].offset = 4;
121 reloc[0].delta = 0;
122 reloc[0].target_handle = handle_target;
123 reloc[0].read_domains = I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION;
124 reloc[0].write_domain = I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION;
125 reloc[0].presumed_offset = 0;
126
127 execbuf.buffers_ptr = to_user_pointer(exec);
128 execbuf.buffer_count = 2;
129 execbuf.batch_start_offset = 0;
130 execbuf.batch_len = 8;
131 execbuf.cliprects_ptr = 0;
132 execbuf.num_cliprects = 0;
133 execbuf.DR1 = 0;
134 execbuf.DR4 = 0;
135 execbuf.flags = 0;
136 i915_execbuffer2_set_context_id(execbuf, 0);
137 execbuf.rsvd2 = 0;
138
139 igt_assert_eq(__gem_execbuf(fd, &execbuf), -EINVAL);
140
141 gem_close(fd, handle);
142 gem_close(fd, handle_target);
143 }
144
145 int fd;
146 drm_intel_bo *tmp;
147
148 igt_main
149 {
150 igt_fixture {
151 fd = drm_open_driver(DRIVER_INTEL);
152 igt_require_gem(fd);
153
154 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
155 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
156 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
157
158 tmp = drm_intel_bo_alloc(bufmgr, "tmp", 128 * 128, 4096);
159 }
160
161 igt_subtest("cpu-domain") {
162 BEGIN_BATCH(2, 1);
163 OUT_BATCH(0);
164 OUT_RELOC(tmp, I915_GEM_DOMAIN_CPU, 0, 0);
165 ADVANCE_BATCH();
166 igt_assert(run_batch() == -EINVAL);
167
168 BEGIN_BATCH(2, 1);
169 OUT_BATCH(0);
170 OUT_RELOC(tmp, I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU, 0);
171 ADVANCE_BATCH();
172 igt_assert(run_batch() == -EINVAL);
173 }
174
175 igt_subtest("gtt-domain") {
176 BEGIN_BATCH(2, 1);
177 OUT_BATCH(0);
178 OUT_RELOC(tmp, I915_GEM_DOMAIN_GTT, 0, 0);
179 ADVANCE_BATCH();
180 igt_assert(run_batch() == -EINVAL);
181
182 BEGIN_BATCH(2, 1);
183 OUT_BATCH(0);
184 OUT_RELOC(tmp, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0);
185 ADVANCE_BATCH();
186 igt_assert(run_batch() == -EINVAL);
187 }
188
189 /* Note: Older kernels disallow this. Punt on the skip check though
190 * since this is too old. */
191 igt_subtest("conflicting-write-domain") {
192 BEGIN_BATCH(4, 2);
193 OUT_BATCH(0);
194 OUT_RELOC(tmp, I915_GEM_DOMAIN_RENDER,
195 I915_GEM_DOMAIN_RENDER, 0);
196 OUT_BATCH(0);
197 OUT_RELOC(tmp, I915_GEM_DOMAIN_INSTRUCTION,
198 I915_GEM_DOMAIN_INSTRUCTION, 0);
199 ADVANCE_BATCH();
200 igt_assert(run_batch() == 0);
201 }
202
203 igt_subtest("double-write-domain")
204 multi_write_domain(fd);
205
206 igt_subtest("invalid-gpu-domain") {
207 BEGIN_BATCH(2, 1);
208 OUT_BATCH(0);
209 OUT_RELOC(tmp, ~(I915_GEM_GPU_DOMAINS | I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU),
210 0, 0);
211 ADVANCE_BATCH();
212 igt_assert(run_batch() == -EINVAL);
213
214 BEGIN_BATCH(2, 1);
215 OUT_BATCH(0);
216 OUT_RELOC(tmp, I915_GEM_DOMAIN_GTT << 1,
217 I915_GEM_DOMAIN_GTT << 1, 0);
218 ADVANCE_BATCH();
219 igt_assert(run_batch() == -EINVAL);
220 }
221
222 igt_fixture {
223 intel_batchbuffer_free(batch);
224 drm_intel_bufmgr_destroy(bufmgr);
225
226 close(fd);
227 }
228 }
229