1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <chris@chris-wilson.co.uk>
25 *
26 */
27
28 #include "igt.h"
29 #include <unistd.h>
30 #include <stdlib.h>
31 #include <stdint.h>
32 #include <stdio.h>
33 #include <string.h>
34 #include <fcntl.h>
35 #include <inttypes.h>
36 #include <errno.h>
37 #include <sys/stat.h>
38 #include <sys/ioctl.h>
39 #include <sys/time.h>
40 #include <sys/wait.h>
41
42 #include "drm.h"
43
44 static const uint32_t canary = 0xdeadbeef;
45
46 typedef struct data {
47 int fd;
48 int devid;
49 int intel_gen;
50 } data_t;
51
elapsed(const struct timeval * start,const struct timeval * end)52 static double elapsed(const struct timeval *start,
53 const struct timeval *end)
54 {
55 return 1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec - start->tv_usec);
56 }
57
busy(data_t * data,uint32_t handle,int size,int loops)58 static void busy(data_t *data, uint32_t handle, int size, int loops)
59 {
60 struct drm_i915_gem_relocation_entry reloc[20];
61 struct drm_i915_gem_exec_object2 gem_exec[2];
62 struct drm_i915_gem_execbuffer2 execbuf;
63 struct drm_i915_gem_pwrite gem_pwrite;
64 struct drm_i915_gem_create create;
65 uint32_t buf[170], *b;
66 int i;
67
68 memset(reloc, 0, sizeof(reloc));
69 memset(gem_exec, 0, sizeof(gem_exec));
70 memset(&execbuf, 0, sizeof(execbuf));
71
72 b = buf;
73 for (i = 0; i < 20; i++) {
74 *b++ = XY_COLOR_BLT_CMD_NOLEN |
75 ((data->intel_gen >= 8) ? 5 : 4) |
76 COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
77 *b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096;
78 *b++ = 0;
79 *b++ = size >> 12 << 16 | 1024;
80 reloc[i].offset = (b - buf) * sizeof(uint32_t);
81 reloc[i].target_handle = handle;
82 reloc[i].read_domains = I915_GEM_DOMAIN_RENDER;
83 reloc[i].write_domain = I915_GEM_DOMAIN_RENDER;
84 *b++ = 0;
85 if (data->intel_gen >= 8)
86 *b++ = 0;
87 *b++ = canary;
88 }
89 *b++ = MI_BATCH_BUFFER_END;
90 if ((b - buf) & 1)
91 *b++ = 0;
92
93 gem_exec[0].handle = handle;
94 gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
95
96 create.handle = 0;
97 create.size = 4096;
98 drmIoctl(data->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
99 gem_exec[1].handle = create.handle;
100 gem_exec[1].relocation_count = 20;
101 gem_exec[1].relocs_ptr = to_user_pointer(reloc);
102
103 execbuf.buffers_ptr = to_user_pointer(gem_exec);
104 execbuf.buffer_count = 2;
105 execbuf.batch_len = (b - buf) * sizeof(buf[0]);
106 execbuf.flags = 1 << 11;
107 if (HAS_BLT_RING(data->devid))
108 execbuf.flags |= I915_EXEC_BLT;
109
110 gem_pwrite.handle = gem_exec[1].handle;
111 gem_pwrite.offset = 0;
112 gem_pwrite.size = execbuf.batch_len;
113 gem_pwrite.data_ptr = to_user_pointer(buf);
114 if (drmIoctl(data->fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) {
115 while (loops--)
116 gem_execbuf(data->fd, &execbuf);
117 }
118
119 drmIoctl(data->fd, DRM_IOCTL_GEM_CLOSE, &create.handle);
120 }
121
run(data_t * data,int child)122 static void run(data_t *data, int child)
123 {
124 const int size = 4096 * (256 + child * child);
125 const int tiling = child % 2;
126 const int write = child % 2;
127 uint32_t handle = gem_create(data->fd, size);
128 uint32_t *ptr;
129 uint32_t x;
130
131 igt_assert(handle);
132
133 if (tiling != I915_TILING_NONE)
134 gem_set_tiling(data->fd, handle, tiling, 4096);
135
136 /* load up the unfaulted bo */
137 busy(data, handle, size, 100);
138
139 /* Note that we ignore the API and rely on the implict
140 * set-to-gtt-domain within the fault handler.
141 */
142 if (write) {
143 ptr = gem_mmap__gtt(data->fd, handle, size,
144 PROT_READ | PROT_WRITE);
145 ptr[rand() % (size / 4)] = canary;
146 } else {
147 ptr = gem_mmap__gtt(data->fd, handle, size, PROT_READ);
148 }
149 x = ptr[rand() % (size / 4)];
150 munmap(ptr, size);
151
152 igt_assert_eq_u32(x, canary);
153 }
154
155 igt_simple_main
156 {
157 struct timeval start, end;
158 pid_t children[64];
159 data_t data = {};
160
161 /* check for an intel gpu before goint nuts. */
162 int fd = drm_open_driver(DRIVER_INTEL);
163 igt_require_gem(fd);
164 close(fd);
165
166 igt_skip_on_simulation();
167
168 data.fd = drm_open_driver(DRIVER_INTEL);
169 data.devid = intel_get_drm_devid(data.fd);
170 data.intel_gen = intel_gen(data.devid);
171
172 gettimeofday(&start, NULL);
173 igt_fork(child, ARRAY_SIZE(children))
174 run(&data, child);
175 igt_waitchildren();
176 gettimeofday(&end, NULL);
177
178 igt_info("Time to execute %zu children: %7.3fms\n",
179 ARRAY_SIZE(children), elapsed(&start, &end) / 1000);
180 }
181