1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 /** @file gem_pread_after_blit.c
29 *
30 * This is a test of pread's behavior when getting values out of just-drawn-to
31 * buffers.
32 *
33 * The goal is to catch failure in the whole-buffer-flush or
34 * ranged-buffer-flush paths in the kernel.
35 */
36
37 #include "igt.h"
38 #include <stdlib.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <fcntl.h>
42 #include <inttypes.h>
43 #include <errno.h>
44 #include <sys/stat.h>
45 #include <sys/time.h>
46
47 #include <drm.h>
48
49
50 IGT_TEST_DESCRIPTION("Test pread behavior when getting values out of"
51 " just-drawn-to buffers.");
52
53 static drm_intel_bufmgr *bufmgr;
54 struct intel_batchbuffer *batch;
55 static const int width = 512, height = 512;
56 static const int size = 1024 * 1024;
57
58 #define PAGE_SIZE 4096
59
60 static drm_intel_bo *
create_bo(uint32_t val)61 create_bo(uint32_t val)
62 {
63 drm_intel_bo *bo;
64 uint32_t *vaddr;
65 int i;
66
67 bo = drm_intel_bo_alloc(bufmgr, "src bo", size, 4096);
68
69 /* Fill the BO with dwords starting at start_val */
70 drm_intel_bo_map(bo, 1);
71 vaddr = bo->virtual;
72
73 for (i = 0; i < 1024 * 1024 / 4; i++)
74 vaddr[i] = val++;
75
76 drm_intel_bo_unmap(bo);
77
78 return bo;
79 }
80
81 static void
verify_large_read(drm_intel_bo * bo,uint32_t val)82 verify_large_read(drm_intel_bo *bo, uint32_t val)
83 {
84 uint32_t buf[size / 4];
85 int i;
86
87 drm_intel_bo_get_subdata(bo, 0, size, buf);
88
89 for (i = 0; i < size / 4; i++) {
90 igt_assert_f(buf[i] == val,
91 "Unexpected value 0x%08x instead of "
92 "0x%08x at offset 0x%08x (%p)\n",
93 buf[i], val, i * 4, buf);
94 val++;
95 }
96 }
97
98 /** This reads at the size that Mesa usees for software fallbacks. */
99 static void
verify_small_read(drm_intel_bo * bo,uint32_t val)100 verify_small_read(drm_intel_bo *bo, uint32_t val)
101 {
102 uint32_t buf[4096 / 4];
103 int offset, i;
104
105 for (i = 0; i < 4096 / 4; i++)
106 buf[i] = 0x00c0ffee;
107
108 for (offset = 0; offset < size; offset += PAGE_SIZE) {
109 drm_intel_bo_get_subdata(bo, offset, PAGE_SIZE, buf);
110
111 for (i = 0; i < PAGE_SIZE; i += 4) {
112 igt_assert_f(buf[i / 4] == val,
113 "Unexpected value 0x%08x instead of "
114 "0x%08x at offset 0x%08x\n",
115 buf[i / 4], val, i * 4);
116 val++;
117 }
118 }
119 }
120
121 typedef igt_hang_t (*do_hang)(int fd);
122
no_hang(int fd)123 static igt_hang_t no_hang(int fd)
124 {
125 return (igt_hang_t){0};
126 }
127
bcs_hang(int fd)128 static igt_hang_t bcs_hang(int fd)
129 {
130 return igt_hang_ring(fd, batch->gen >= 6 ? I915_EXEC_BLT : I915_EXEC_DEFAULT);
131 }
132
do_test(int fd,int cache_level,drm_intel_bo * src[2],const uint32_t start[2],drm_intel_bo * tmp[2],int loop,do_hang do_hang_func)133 static void do_test(int fd, int cache_level,
134 drm_intel_bo *src[2],
135 const uint32_t start[2],
136 drm_intel_bo *tmp[2],
137 int loop, do_hang do_hang_func)
138 {
139 igt_hang_t hang;
140
141 if (cache_level != -1) {
142 gem_set_caching(fd, tmp[0]->handle, cache_level);
143 gem_set_caching(fd, tmp[1]->handle, cache_level);
144 }
145
146 do {
147 /* First, do a full-buffer read after blitting */
148 intel_copy_bo(batch, tmp[0], src[0], width*height*4);
149 hang = do_hang_func(fd);
150 verify_large_read(tmp[0], start[0]);
151 igt_post_hang_ring(fd, hang);
152 intel_copy_bo(batch, tmp[0], src[1], width*height*4);
153 hang = do_hang_func(fd);
154 verify_large_read(tmp[0], start[1]);
155 igt_post_hang_ring(fd, hang);
156
157 intel_copy_bo(batch, tmp[0], src[0], width*height*4);
158 hang = do_hang_func(fd);
159 verify_small_read(tmp[0], start[0]);
160 igt_post_hang_ring(fd, hang);
161 intel_copy_bo(batch, tmp[0], src[1], width*height*4);
162 hang = do_hang_func(fd);
163 verify_small_read(tmp[0], start[1]);
164 igt_post_hang_ring(fd, hang);
165
166 intel_copy_bo(batch, tmp[0], src[0], width*height*4);
167 hang = do_hang_func(fd);
168 verify_large_read(tmp[0], start[0]);
169 igt_post_hang_ring(fd, hang);
170
171 intel_copy_bo(batch, tmp[0], src[0], width*height*4);
172 intel_copy_bo(batch, tmp[1], src[1], width*height*4);
173 hang = do_hang_func(fd);
174 verify_large_read(tmp[0], start[0]);
175 verify_large_read(tmp[1], start[1]);
176 igt_post_hang_ring(fd, hang);
177
178 intel_copy_bo(batch, tmp[0], src[0], width*height*4);
179 intel_copy_bo(batch, tmp[1], src[1], width*height*4);
180 hang = do_hang_func(fd);
181 verify_large_read(tmp[1], start[1]);
182 verify_large_read(tmp[0], start[0]);
183 igt_post_hang_ring(fd, hang);
184
185 intel_copy_bo(batch, tmp[1], src[0], width*height*4);
186 intel_copy_bo(batch, tmp[0], src[1], width*height*4);
187 hang = do_hang_func(fd);
188 verify_large_read(tmp[0], start[1]);
189 verify_large_read(tmp[1], start[0]);
190 igt_post_hang_ring(fd, hang);
191 } while (--loop);
192 }
193
194 drm_intel_bo *src[2], *dst[2];
195 int fd;
196
197 igt_main
198 {
199 const uint32_t start[2] = {0, 1024 * 1024 / 4};
200 const struct {
201 const char *name;
202 int cache;
203 } tests[] = {
204 { "default", -1 },
205 { "uncached", 0 },
206 { "snooped", 1 },
207 { "display", 2 },
208 { NULL, -1 },
209 }, *t;
210
211 igt_skip_on_simulation();
212
213 igt_fixture {
214 fd = drm_open_driver(DRIVER_INTEL);
215 igt_require_gem(fd);
216
217 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
218 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
219 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
220
221 src[0] = create_bo(start[0]);
222 src[1] = create_bo(start[1]);
223
224 dst[0] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
225 dst[1] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
226 }
227
228 for (t = tests; t->name; t++) {
229 igt_subtest_f("%s-normal", t->name)
230 do_test(fd, t->cache, src, start, dst, 1, no_hang);
231
232 igt_fork_signal_helper();
233 igt_subtest_f("%s-interruptible", t->name)
234 do_test(fd, t->cache, src, start, dst, 100, no_hang);
235 igt_stop_signal_helper();
236
237 igt_subtest_f("%s-hang", t->name)
238 do_test(fd, t->cache, src, start, dst, 1, bcs_hang);
239 }
240
241 igt_fixture {
242 drm_intel_bo_unreference(src[0]);
243 drm_intel_bo_unreference(src[1]);
244 drm_intel_bo_unreference(dst[0]);
245 drm_intel_bo_unreference(dst[1]);
246
247 intel_batchbuffer_free(batch);
248 drm_intel_bufmgr_destroy(bufmgr);
249 }
250
251 igt_fixture
252 close(fd);
253 }
254