1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 /** @file gem_tiled_blits.c
29 *
30 * This is a test of doing many tiled blits, with a working set
31 * larger than the aperture size.
32 *
33 * The goal is to catch a couple types of failure;
34 * - Fence management problems on pre-965.
35 * - A17 or L-shaped memory tiling workaround problems in acceleration.
36 *
37 * The model is to fill a collection of 1MB objects in a way that can't trip
38 * over A6 swizzling -- upload data to a non-tiled object, blit to the tiled
39 * object. Then, copy the 1MB objects randomly between each other for a while.
40 * Finally, download their data through linear objects again and see what
41 * resulted.
42 */
43
44 #include "igt.h"
45 #include <stdlib.h>
46 #include <stdio.h>
47 #include <string.h>
48 #include <fcntl.h>
49 #include <inttypes.h>
50 #include <errno.h>
51 #include <sys/stat.h>
52 #include <sys/time.h>
53
54 #include <drm.h>
55
56
57 IGT_TEST_DESCRIPTION("Test doing many tiled blits, with a working set larger"
58 " than the aperture size.");
59
60 static drm_intel_bufmgr *bufmgr;
61 struct intel_batchbuffer *batch;
62 static int width = 512, height = 512;
63
64 static drm_intel_bo *
create_bo(uint32_t start_val)65 create_bo(uint32_t start_val)
66 {
67 drm_intel_bo *bo, *linear_bo;
68 uint32_t *linear;
69 uint32_t tiling = I915_TILING_X;
70 int i;
71
72 bo = drm_intel_bo_alloc(bufmgr, "tiled bo", 1024 * 1024, 4096);
73 do_or_die(drm_intel_bo_set_tiling(bo, &tiling, width * 4));
74 igt_assert(tiling == I915_TILING_X);
75
76 linear_bo = drm_intel_bo_alloc(bufmgr, "linear src", 1024 * 1024, 4096);
77
78 /* Fill the BO with dwords starting at start_val */
79 do_or_die(drm_intel_bo_map(linear_bo, 1));
80 linear = linear_bo->virtual;
81 for (i = 0; i < 1024 * 1024 / 4; i++)
82 linear[i] = start_val++;
83 drm_intel_bo_unmap(linear_bo);
84
85 intel_copy_bo (batch, bo, linear_bo, width*height*4);
86
87 drm_intel_bo_unreference(linear_bo);
88
89 return bo;
90 }
91
92 static void
check_bo(drm_intel_bo * bo,uint32_t val)93 check_bo(drm_intel_bo *bo, uint32_t val)
94 {
95 drm_intel_bo *linear_bo;
96 uint32_t *linear;
97 int num_errors;
98 int i;
99
100 linear_bo = drm_intel_bo_alloc(bufmgr, "linear dst", 1024 * 1024, 4096);
101
102 intel_copy_bo(batch, linear_bo, bo, width*height*4);
103
104 do_or_die(drm_intel_bo_map(linear_bo, 0));
105 linear = linear_bo->virtual;
106
107 num_errors = 0;
108 for (i = 0; i < 1024 * 1024 / 4; i++) {
109 if (linear[i] != val && num_errors++ < 32)
110 igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n",
111 i * 4, val, linear[i], val ^ linear[i]);
112 val++;
113 }
114 igt_assert_eq(num_errors, 0);
115 drm_intel_bo_unmap(linear_bo);
116
117 drm_intel_bo_unreference(linear_bo);
118 }
119
run_test(int count)120 static void run_test(int count)
121 {
122 drm_intel_bo **bo;
123 uint32_t *bo_start_val;
124 uint32_t start = 0;
125 int i;
126
127 igt_debug("Using %d 1MiB buffers\n", count);
128
129 bo = malloc(sizeof(drm_intel_bo *)*count);
130 bo_start_val = malloc(sizeof(uint32_t)*count);
131
132 for (i = 0; i < count; i++) {
133 bo[i] = create_bo(start);
134 bo_start_val[i] = start;
135 start += 1024 * 1024 / 4;
136 }
137 igt_info("Verifying initialisation...\n");
138 for (i = 0; i < count; i++)
139 check_bo(bo[i], bo_start_val[i]);
140
141 igt_info("Cyclic blits, forward...\n");
142 for (i = 0; i < count * 4; i++) {
143 int src = i % count;
144 int dst = (i+1) % count;
145
146 if (src == dst)
147 continue;
148
149 intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
150 bo_start_val[dst] = bo_start_val[src];
151 }
152 for (i = 0; i < count; i++)
153 check_bo(bo[i], bo_start_val[i]);
154
155 if (igt_run_in_simulation()) {
156 for (i = 0; i < count; i++)
157 drm_intel_bo_unreference(bo[i]);
158 free(bo_start_val);
159 free(bo);
160 return;
161 }
162
163 igt_info("Cyclic blits, backward...\n");
164 for (i = 0; i < count * 4; i++) {
165 int src = (i+1) % count;
166 int dst = i % count;
167
168 if (src == dst)
169 continue;
170
171 intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
172 bo_start_val[dst] = bo_start_val[src];
173 }
174 for (i = 0; i < count; i++)
175 check_bo(bo[i], bo_start_val[i]);
176
177 igt_info("Random blits...\n");
178 for (i = 0; i < count * 4; i++) {
179 int src = random() % count;
180 int dst = random() % count;
181
182 if (src == dst)
183 continue;
184
185 intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
186 bo_start_val[dst] = bo_start_val[src];
187 }
188 for (i = 0; i < count; i++) {
189 check_bo(bo[i], bo_start_val[i]);
190 drm_intel_bo_unreference(bo[i]);
191 }
192
193 free(bo_start_val);
194 free(bo);
195 }
196
197 #define MAX_32b ((1ull << 32) - 4096)
198
199 int fd;
200
201 igt_main
202 {
203 igt_fixture {
204 fd = drm_open_driver(DRIVER_INTEL);
205 igt_require_gem(fd);
206
207 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
208 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
209 drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 32);
210 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
211 }
212
213 igt_subtest("basic")
214 run_test(2);
215
216 igt_subtest("normal") {
217 uint64_t count;
218
219 count = gem_aperture_size(fd);
220 if (count >> 32)
221 count = MAX_32b;
222 count = 3 * count / (1024*1024) / 2;
223 count += (count & 1) == 0;
224 intel_require_memory(count, 1024*1024, CHECK_RAM);
225
226 run_test(count);
227 }
228
229 igt_subtest("interruptible") {
230 uint64_t count;
231
232 count = gem_aperture_size(fd);
233 if (count >> 32)
234 count = MAX_32b;
235 count = 3 * count / (1024*1024) / 2;
236 count += (count & 1) == 0;
237 intel_require_memory(count, 1024*1024, CHECK_RAM);
238
239 igt_fork_signal_helper();
240 run_test(count);
241 igt_stop_signal_helper();
242 }
243
244 igt_fixture {
245 intel_batchbuffer_free(batch);
246 drm_intel_bufmgr_destroy(bufmgr);
247
248 close(fd);
249 }
250 }
251