1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
25 *
26 */
27
28 #include "igt.h"
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <string.h>
32 #include <fcntl.h>
33 #include <inttypes.h>
34 #include <errno.h>
35 #include <sys/stat.h>
36 #include <sys/time.h>
37
38 #include <drm.h>
39
40 #include "i830_reg.h"
41
42 IGT_TEST_DESCRIPTION("Check read/write syncpoints when switching rings.");
43
44 #define LOCAL_I915_EXEC_VEBOX (4<<0)
45
46 static drm_intel_bufmgr *bufmgr;
47 struct intel_batchbuffer *batch;
48 static drm_intel_bo *load_bo, *target_bo, *dummy_bo;
49 int fd;
50
51 /* Testcase: check read/write syncpoints when switching rings
52 *
53 * We've had a bug where the syncpoint for the last write was mangled after a
54 * ring switch using semaphores. This resulted in cpu reads returning before the
55 * write actually completed. This test exercises this.
56 */
57
58 #define COLOR 0xffffffff
run_test(int ring)59 static void run_test(int ring)
60 {
61 uint32_t *ptr;
62 int i;
63
64 gem_require_ring(fd, ring);
65 /* Testing render only makes sense with separate blt. */
66 if (ring == I915_EXEC_RENDER)
67 gem_require_ring(fd, I915_EXEC_BLT);
68
69 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
70 igt_assert(target_bo);
71
72 /* Need to map first so that we can do our own domain mangement with
73 * set_domain. */
74 drm_intel_bo_map(target_bo, 0);
75 ptr = target_bo->virtual;
76 igt_assert(*ptr == 0);
77
78 /* put some load onto the gpu to keep the light buffers active for long
79 * enough */
80 for (i = 0; i < 1000; i++) {
81 BLIT_COPY_BATCH_START(0);
82 OUT_BATCH((3 << 24) | /* 32 bits */
83 (0xcc << 16) | /* copy ROP */
84 4096);
85 OUT_BATCH(0); /* dst x1,y1 */
86 OUT_BATCH((1024 << 16) | 512);
87 OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
88 OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
89 OUT_BATCH(4096);
90 OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
91 ADVANCE_BATCH();
92 }
93
94 COLOR_BLIT_COPY_BATCH_START(0);
95 OUT_BATCH((3 << 24) | /* 32 bits */
96 (0xff << 16) |
97 128);
98 OUT_BATCH(0); /* dst x1,y1 */
99 OUT_BATCH((1 << 16) | 1);
100 OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
101 OUT_BATCH(COLOR);
102 ADVANCE_BATCH();
103
104 intel_batchbuffer_flush(batch);
105
106 /* Emit an empty batch so that signalled seqno on the target ring >
107 * signalled seqnoe on the blt ring. This is required to hit the bug. */
108 BEGIN_BATCH(2, 0);
109 OUT_BATCH(MI_NOOP);
110 OUT_BATCH(MI_NOOP);
111 ADVANCE_BATCH();
112 intel_batchbuffer_flush_on_ring(batch, ring);
113
114 /* For the ring->ring sync it's important to only emit a read reloc, for
115 * otherwise the obj->last_write_seqno will be updated. */
116 if (ring == I915_EXEC_RENDER) {
117 BEGIN_BATCH(4, 1);
118 OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
119 OUT_BATCH(0xffffffff); /* compare dword */
120 OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
121 OUT_BATCH(MI_NOOP);
122 ADVANCE_BATCH();
123 } else {
124 BEGIN_BATCH(4, 1);
125 OUT_BATCH(MI_FLUSH_DW | 1);
126 OUT_BATCH(0); /* reserved */
127 OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
128 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
129 ADVANCE_BATCH();
130 }
131 intel_batchbuffer_flush_on_ring(batch, ring);
132
133 gem_set_domain(fd, target_bo->handle, I915_GEM_DOMAIN_GTT, 0);
134 igt_assert(*ptr == COLOR);
135 drm_intel_bo_unmap(target_bo);
136
137 drm_intel_bo_unreference(target_bo);
138 }
139
140 igt_main
141 {
142 static const struct {
143 const char *name;
144 int ring;
145 } tests[] = {
146 { "blt2render", I915_EXEC_RENDER },
147 { "blt2bsd", I915_EXEC_BSD },
148 { "blt2vebox", LOCAL_I915_EXEC_VEBOX },
149 };
150 int i;
151
152 igt_skip_on_simulation();
153
154 igt_fixture {
155 fd = drm_open_driver(DRIVER_INTEL);
156 igt_require_gem(fd);
157
158 /* Test requires MI_FLUSH_DW and MI_COND_BATCH_BUFFER_END */
159 igt_require(intel_gen(intel_get_drm_devid(fd)) >= 6);
160
161 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
162 igt_assert(bufmgr);
163 /* don't enable buffer reuse!! */
164 //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
165
166 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
167 igt_assert(batch);
168
169 dummy_bo = drm_intel_bo_alloc(bufmgr, "dummy bo", 4096, 4096);
170 igt_assert(dummy_bo);
171
172 load_bo = drm_intel_bo_alloc(bufmgr, "load bo", 1024*4096, 4096);
173 igt_assert(load_bo);
174 }
175
176 for (i = 0; i < ARRAY_SIZE(tests); i++) {
177 igt_subtest(tests[i].name)
178 run_test(tests[i].ring);
179 }
180
181 igt_fork_signal_helper();
182 for (i = 0; i < ARRAY_SIZE(tests); i++) {
183 igt_subtest_f("%s-interruptible", tests[i].name)
184 run_test(tests[i].ring);
185 }
186 igt_stop_signal_helper();
187
188 igt_fixture {
189 drm_intel_bufmgr_destroy(bufmgr);
190
191 close(fd);
192 }
193 }
194