1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include "igt.h"
26 #include <errno.h>
27 #include <limits.h>
28 #include <stdbool.h>
29 #include <stdio.h>
30 #include <string.h>
31
32
33 IGT_TEST_DESCRIPTION("Exercises full ppgtt fence pin_count leak in the "
34 "kernel.");
35
36 typedef struct {
37 int drm_fd;
38 uint32_t devid;
39 drm_intel_bufmgr *bufmgr;
40 igt_display_t display;
41 drm_intel_bo *bos[64]; /* >= num fence registers */
42 } data_t;
43
exec_nop(data_t * data,uint32_t handle,drm_intel_context * context)44 static void exec_nop(data_t *data, uint32_t handle, drm_intel_context *context)
45 {
46 drm_intel_bo *dst;
47 struct intel_batchbuffer *batch;
48
49 dst = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, "", handle);
50 igt_assert(dst);
51
52 batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
53 igt_assert(batch);
54
55 /* add the reloc to make sure the kernel will think we write to dst */
56 BEGIN_BATCH(4, 1);
57 OUT_BATCH(MI_BATCH_BUFFER_END);
58 OUT_BATCH(MI_NOOP);
59 OUT_RELOC(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
60 OUT_BATCH(MI_NOOP);
61 ADVANCE_BATCH();
62
63 intel_batchbuffer_flush_with_context(batch, context);
64 intel_batchbuffer_free(batch);
65
66 drm_intel_bo_unreference(dst);
67 }
68
alloc_fence_objs(data_t * data)69 static void alloc_fence_objs(data_t *data)
70 {
71 int i;
72
73 for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
74 drm_intel_bo *bo;
75
76 bo = drm_intel_bo_alloc(data->bufmgr, "fence bo", 4096, 4096);
77 igt_assert(bo);
78 gem_set_tiling(data->drm_fd, bo->handle, I915_TILING_X, 512);
79
80 data->bos[i] = bo;
81 }
82 }
83
touch_fences(data_t * data)84 static void touch_fences(data_t *data)
85 {
86 int i;
87
88 for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
89 uint32_t handle = data->bos[i]->handle;
90 void *ptr;
91
92 ptr = gem_mmap__gtt(data->drm_fd, handle, 4096, PROT_WRITE);
93 gem_set_domain(data->drm_fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
94 memset(ptr, 0, 4);
95 munmap(ptr, 4096);
96 }
97 }
98
free_fence_objs(data_t * data)99 static void free_fence_objs(data_t *data)
100 {
101 int i;
102
103 for (i = 0; i < ARRAY_SIZE(data->bos); i++)
104 drm_intel_bo_unreference(data->bos[i]);
105 }
106
run_single_test(data_t * data,enum pipe pipe,igt_output_t * output)107 static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
108 {
109 igt_display_t *display = &data->display;
110 drmModeModeInfo *mode;
111 igt_plane_t *primary;
112 struct igt_fb fb[2];
113 int i;
114
115 igt_output_set_pipe(output, pipe);
116
117 mode = igt_output_get_mode(output);
118 primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
119
120 igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
121 DRM_FORMAT_XRGB8888,
122 LOCAL_I915_FORMAT_MOD_X_TILED , /* need a fence so must be tiled */
123 0.0, 0.0, 0.0,
124 &fb[0]);
125 igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
126 DRM_FORMAT_XRGB8888,
127 LOCAL_I915_FORMAT_MOD_X_TILED, /* need a fence so must be tiled */
128 0.0, 0.0, 0.0,
129 &fb[1]);
130
131 igt_plane_set_fb(primary, &fb[0]);
132 igt_display_commit(display);
133
134 for (i = 0; i < 64; i++) {
135 drm_intel_context *ctx;
136
137 /*
138 * Link fb.gem_handle to the ppgtt vm of ctx so that the context
139 * destruction will unbind the obj from the ppgtt vm in question.
140 */
141 ctx = drm_intel_gem_context_create(data->bufmgr);
142 igt_assert(ctx);
143 exec_nop(data, fb[i&1].gem_handle, ctx);
144 drm_intel_gem_context_destroy(ctx);
145
146 /* Force a context switch to make sure ctx gets destroyed for real. */
147 exec_nop(data, fb[i&1].gem_handle, NULL);
148
149 gem_sync(data->drm_fd, fb[i&1].gem_handle);
150
151 /*
152 * Make only the current fb has a fence and
153 * the next fb will pick a new fence. Assuming
154 * all fences are associated with an object, the
155 * kernel will always pick a fence with pin_count==0.
156 */
157 touch_fences(data);
158
159 /*
160 * Pin the new buffer and unpin the old buffer from display. If
161 * the kernel is buggy the ppgtt unbind will have dropped the
162 * fence for the old buffer, and now the display code will try
163 * to unpin only to find no fence there. So the pin_count will leak.
164 */
165 igt_plane_set_fb(primary, &fb[!(i&1)]);
166 igt_display_commit(display);
167
168 igt_print_activity();
169 }
170
171 igt_plane_set_fb(primary, NULL);
172 igt_output_set_pipe(output, PIPE_ANY);
173 igt_display_commit(display);
174
175 igt_remove_fb(data->drm_fd, &fb[1]);
176 igt_remove_fb(data->drm_fd, &fb[0]);
177
178 igt_info("\n");
179 }
180
run_test(data_t * data)181 static void run_test(data_t *data)
182 {
183 igt_display_t *display = &data->display;
184 igt_output_t *output;
185 enum pipe p;
186
187 for_each_pipe_with_valid_output(display, p, output) {
188 run_single_test(data, p, output);
189
190 return; /* one time ought to be enough */
191 }
192
193 igt_skip("no valid crtc/connector combinations found\n");
194 }
195
196 igt_simple_main
197 {
198 drm_intel_context *ctx;
199 data_t data = {};
200
201 igt_skip_on_simulation();
202
203 data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
204 igt_require_gem(data.drm_fd);
205
206 data.devid = intel_get_drm_devid(data.drm_fd);
207
208 kmstest_set_vt_graphics_mode();
209
210 data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
211 igt_assert(data.bufmgr);
212 drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
213
214 igt_display_require(&data.display, data.drm_fd);
215
216 ctx = drm_intel_gem_context_create(data.bufmgr);
217 igt_require(ctx);
218 drm_intel_gem_context_destroy(ctx);
219
220 alloc_fence_objs(&data);
221
222 run_test(&data);
223
224 free_fence_objs(&data);
225
226 drm_intel_bufmgr_destroy(data.bufmgr);
227 igt_display_fini(&data.display);
228 }
229